- •About This Manual
- •Additional Resources
- •Manual Contents
- •Conventions
- •Typographical
- •Online Document
- •Using Foundation Express with VHDL
- •Hardware Description Languages
- •Typical Uses for HDLs
- •Advantages of HDLs
- •About VHDL
- •Foundation Express Design Process
- •Using Foundation Express to Compile a VHDL Design
- •Design Methodology
- •Design Descriptions
- •Entities
- •Entity Generic Specifications
- •Entity Port Specifications
- •Architecture
- •Declarations
- •Components
- •Concurrent Statements
- •Constant Declarations
- •Processes
- •Signal Declarations
- •Subprograms
- •Type Declarations
- •Examples of Architectures for NAND2 Entity
- •Configurations
- •Packages
- •Using a Package
- •Package Structure
- •Package Declarations
- •Package Body
- •Resolution Functions
- •Data Types
- •Type Overview
- •Enumeration Types
- •Enumeration Overloading
- •Enumeration Encoding
- •Enumeration Encoding Values
- •Integer Types
- •Array Types
- •Constrained Array
- •Unconstrained Array
- •Array Attributes
- •Record Types
- •Record Aggregates
- •Predefined VHDL Data Types
- •Data Type BOOLEAN
- •Data Type BIT
- •Data Type CHARACTER
- •Data Type INTEGER
- •Data Type NATURAL
- •Data Type POSITIVE
- •Data Type STRING
- •Data Type BIT_VECTOR
- •Unsupported Data Types
- •Physical Types
- •Floating-Point Types
- •Access Types
- •File Types
- •Express Data Types
- •Subtypes
- •Expressions
- •Overview
- •Operators
- •Logical Operators
- •Relational Operators
- •Adding Operators
- •Unary (Signed) Operators
- •Multiplying Operators
- •Miscellaneous Arithmetic Operators
- •Operands
- •Operand Bit-Width
- •Computable Operands
- •Aggregates
- •Attributes
- •Expressions
- •Function Calls
- •Identifiers
- •Indexed Names
- •Literals
- •Numeric Literals
- •Character Literals
- •Enumeration Literals
- •String Literals
- •Qualified Expressions
- •Records and Fields
- •Slice Names
- •Limitations on Null Slices
- •Limitations on Noncomputable Slices
- •Type Conversions
- •Sequential Statements
- •Assignment Statements and Targets
- •Simple Name Targets
- •Indexed Name Targets
- •Slice Targets
- •Field Targets
- •Aggregate Targets
- •Variable Assignment Statements
- •Signal Assignment Statements
- •Variable Assignment
- •Signal Assignment
- •if Statements
- •Evaluating Conditions
- •Using the if Statement to Infer Registers and Latches
- •case Statements
- •Using Different Expression Types
- •Invalid case Statements
- •loop Statements
- •Basic loop Statement
- •while...loop Statements
- •for...loop Statements
- •Steps in the Execution of a for...loop Statement
- •for...loop Statements and Arrays
- •next Statements
- •exit Statements
- •Subprograms
- •Subprogram Always a Combinatorial Circuit
- •Subprogram Declaration and Body
- •Subprogram Calls
- •Procedure Calls
- •Function Calls
- •return Statements
- •Procedures and Functions as Design Components
- •Example with Component Implication Directives
- •Example without Component Implication Directives
- •wait Statements
- •Inferring Synchronous Logic
- •Combinatorial Versus Sequential Processes
- •null Statements
- •Concurrent Statements
- •Overview
- •process Statements
- •Combinatorial Process Example
- •Sequential Process Example
- •Driving Signals
- •block Statements
- •Nested Blocks
- •Guarded Blocks
- •Concurrent Versions of Sequential Statements
- •Concurrent Procedure Calls
- •Concurrent Signal Assignments
- •Simple Concurrent Signal Assignments
- •Conditional Signal Assignments
- •Selected Signal Assignments
- •Component Instantiation Statements
- •Direct Instantiation
- •generate Statements
- •for...generate Statements
- •Steps in the Execution of a for...generate Statement
- •Common Usage of a for...generate Statement
- •if...generate Statements
- •Register and Three-State Inference
- •Register Inference
- •The Inference Report
- •Latch Inference Warnings
- •Controlling Register Inference
- •Inferring Latches
- •Inferring Set/Reset (SR) Latches
- •Inferring D Latches
- •Inferring Master-Slave Latches
- •Inferring Flip-Flops
- •Inferring D Flip-Flops
- •Inferring JK Flip-Flops
- •Inferring Toggle Flip-Flops
- •Getting the Best Results
- •Understanding Limitations of Register Inference
- •Three-State Inference
- •Reporting Three-State Inference
- •Controlling Three-State Inference
- •Inferring Three-State Drivers
- •Inferring a Simple Three-State Driver
- •Three-State Driver with Registered Enable
- •Three-State Driver Without Registered Enable
- •Writing Circuit Descriptions
- •How Statements Are Mapped to Logic
- •Design Structure
- •Adding Structure
- •Using Variables and Signals
- •Using Parentheses
- •Using Design Knowledge
- •Optimizing Arithmetic Expressions
- •Arranging Expression Trees for Minimum Delay
- •Sharing Common Subexpressions
- •Changing an Operator Bit-Width
- •Using State Information
- •Propagating Constants
- •Sharing Complex Operators
- •Asynchronous Designs
- •Don’t Care Inference
- •Using Don’t Care Default Values
- •Differences Between Simulation and Synthesis
- •Synthesis Issues
- •Feedback Paths and Latches
- •Fully Specified Variables
- •Asynchronous Behavior
- •Understanding Superset Issues and Error Checking
- •Foundation Express Directives
- •Notation for Foundation Express Directives
- •Foundation Express Directives
- •Translation Stop and Start Pragma Directives
- •synthesis_off and synthesis_on Directives
- •Resolution Function Directives
- •Component Implication Directives
- •Foundation Express Packages
- •std_logic_1164 Package
- •std_logic_arith Package
- •Using the Package
- •Modifying the Package
- •Data Types
- •UNSIGNED
- •SIGNED
- •Conversion Functions
- •Arithmetic Functions
- •Example 10-1: Binary Arithmetic Functions
- •Example 10-2: Unary Arithmetic Functions
- •Comparison Functions
- •Example 10-3: Ordering Functions
- •Example 10-4: Equality Functions
- •Shift Functions
- •ENUM_ENCODING Attribute
- •pragma built_in
- •Type Conversion
- •numeric_std Package
- •Understanding the Limitations of numeric_std package
- •Using the Package
- •Data Types
- •Conversion Functions
- •Resize Function
- •Arithmetic Functions
- •Comparison Functions
- •Defining Logical Operators Functions
- •Shift Functions
- •Rotate Functions
- •Shift and Rotate Operators
- •std_logic_misc Package
- •ATTRIBUTES Package
- •VHDL Constructs
- •VHDL Construct Support
- •Design Units
- •Data Types
- •Declarations
- •Specifications
- •Names
- •Identifiers and Extended Identifiers
- •Specifics of Identifiers
- •Specifics of Extended Identifiers
- •Operators
- •Shift and Rotate Operators
- •xnor Operator
- •Operands and Expressions
- •Sequential Statements
- •Concurrent Statements
- •Predefined Language Environment
- •VHDL Reserved Words
- •Examples
- •Moore Machine
- •Mealy Machine
- •Read-Only Memory
- •Waveform Generator
- •Smart Waveform Generator
- •Definable-Width Adder-Subtracter
- •Count Zeros—Combinatorial Version
- •Count Zeros—Sequential Version
- •Soft Drink Machine—State Machine Version
- •Soft Drink Machine—Count Nickels Version
- •Carry-Lookahead Adder
- •Carry Value Computations
- •Implementation
- •Serial-to-Parallel Converter—Counting Bits
- •Input Format
- •Implementation Details
- •Serial-to-Parallel Converter—Shifting Bits
- •Programmable Logic Arrays
Data Types
strained array type definition from the previous “Unconstrained Array” section.
Table 3-1 Array Index Attributes
Attribute Expression |
Value |
MY_VECTOR’left |
5 |
MY_VECTOR’right |
-5 |
MY_VECTOR’high |
5 |
MY_VECTOR’low |
5 |
MY_VECTOR’length |
11 |
MY_VECTOR’range |
(5 down to -5) |
MY_VECTOR’reverse_range |
(-5 to 5) |
The following example shows the use of array attributes in a function that ORs together all elements of a given bit vector (declared in the example of an unconstrained array type definition in the previous section) and returns that value.
function OR_ALL (X: in BIT_VECTOR) return BIT is variable OR_BIT: BIT;
begin
OR_BIT := ’0’;
for I in X’range loop OR_BIT := OR_BIT or X(I);
end loop;
return OR_BIT; end;
Note: This function works for a bit vector of any size.
Record Types
A record is a set of named fields of various types, unlike an array, which is composed of identical anonymous entries. A record’s field can be any previously defined type, including another record type.
The following example shows a record type declaration (BYTE_AND_IX), three signals of that type, and some assignments.
constant LEN: INTEGER := 8;
subtype BYTE_VEC is BIT_VECTOR(LEN-1 downto 0);
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type BYTE_AND_IX is record
BYTE: BYTE_VEC;
IX: INTEGER range 0 to LEN; end record;
signal X, Y, Z: BYTE_AND_IX;
signal DATA: BYTE_VEC; signal NUM: INTEGER;
. . .
X.BYTE <= "11110000";
X.IX <= 2;
DATA <= Y.BYTE;
NUM <= Y.IX;
Z <= X;
As shown in the above example, you can read values from or assign values to records in two ways.
•By individual field name
X.BYTE <= DATA;
X.IX <= LEN;
•From another record object of the same type
Z <= X;
The individual fields of a record type object are accessed by the object name, a period, and a field name; X.BYTE or X.IX. To access an element of the BYTE field’s array, use the array notation X.BYTE(2).
Record Aggregates
Record aggregates (constants) have the same syntax as array aggregates (see the “Aggregates” section of the “Expressions” chapter). They can appear anywhere records appear.
The following line illustrates a named record aggregate in a description.
X <= (BYTE => "11110000", IX => 2);
The following line illustrates a positional record aggregate in a description.
X <= ("11110000", 2);
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Data Types
You can use the others construct in a named or positional record aggregate, just as you can in an array aggregate (see the “Aggregates” section of the “Expressions” chapter).
You can mix named and positional aggregates in a description, with the positional items listed first.
You cannot have a named item that refers to a field covered in the positional aggregate. The following four examples illustrate this caveat.
The following example shows a simple record type.
type rec is record
a:integer;
b:integer;
c:integer;
d:integer;
e:integer; end record
end
The following example shows a named aggregate for the previous example.
(a => 1, b => 2, c => 0, d => 3, e => 0)
In a named aggregate, the items can appear in any order as shown in the following example.
(1, 2, d => 3, others => 0)
The previous example is equivalent to the second example or the following example of positional aggregate.
(1, 2, 0, 3, 0)
You can supply a set of choices in a description of a record aggregate, but a choice cannot be a range. See the following two examples.
The following example shows a record aggregate equivalent to the next example after it.
(b => 2, c => 2, d => 2, a => 1, e => 3)
The following example shows a record aggregate with a set of choices.
(b | c | d => 2, a => 1, e =>3)
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