VHDL Reference Guide

Type Overview

The advantage of strong typing is that VHDL tools can detect many common design errors, such as assigning an 8-bit value to a 4-bit-wide signal or incrementing an array index out of its range.

The following example code shows the definition of a new type, BYTE, as an array of 8 bits, and a variable declaration, ADDEND, that uses this type.

type BYTE is array(7 downto 0) of BIT; variable ADDEND: BYTE;

The predefined VHDL data types are built from the basic VHDL data types. Some VHDL types are not supported for synthesis, such as REAL and FILE.

The examples in this chapter show type definitions and associated object declarations. Although each constant, signal, variable, function, and parameter is declared with a type, only variable and signal declarations are shown in this chapter’s examples. Constant, function, and parameter declarations are shown in the “Declarations” section of the “Design Descriptions” chapter.

VHDL also provides subtypes, which are defined as subsets of other types. Anywhere a type definition can appear, a subtype definition can also appear. The difference between a type and a subtype is that a subtype is a subset of a previously defined parent (or base) type or subtype. Overlapping subtypes of a given base type can be compared against and assigned to each other. All integer types, for example, are technically subtypes of the built-in integer base type (see the “Integer Types” section and “Subtypes” section of this chapter).

Enumeration Types

You define an enumeration type by listing (enumerating) all possible values of that type.

The syntax of an enumeration type definition follows.

type type_name is ( enumeration_literal {, enumeration_literal} );

•type_name is an identifier

•Each enumeration_literal is either an identifier (enum_6) or a character literal (’A’).

Data Types

•An identifier is a sequence of letters, underscores, and numbers. An identifier must start with a letter and cannot be a VHDL reserved word, such as TYPE. All VHDL reserved words are listed in the “VHDL Construct Support” section of the “VHDL Constructs” chapter.

A character literal is any value of type CHARACTER, in single quotes.

The following example shows two enumeration type definitions and the corresponding variable and signal declarations.

type COLOR is (BLUE, GREEN, YELLOW, RED); type MY_LOGIC is (’0’, ’1’, ’U’, ’Z’); variable HUE: COLOR;

signal SIG: MY_LOGIC;

. . .

HUE := BLUE;

SIG <= ’Z’;

Enumeration Overloading

You can overload an enumeration literal by including it in the definition of two or more enumeration types. When you use such an overloaded enumeration literal, Foundation Express can usually determine the literal’s type. However, under certain circumstances, determination may be impossible. In these cases, you must qualify the literal by explicitly stating its type. (See the “Enumeration Literals” section of the “Expressions” chapter.) The following example shows how you can qualify an overloaded enumeration literal.

type COLOR is (RED, GREEN, YELLOW, BLUE, VIOLET); type PRIMARY_COLOR is (RED, YELLOW, BLUE);

...

A <= COLOR’(RED);

Enumeration Encoding

Enumeration types are ordered by enumeration value. By default, the first enumeration literal is assigned the value 0, the next enumeration literal is assigned the value 1, and so forth.

Foundation Express automatically encodes enumeration values into bit vectors that are based on each value’s position. The length of the

VHDL Reference Guide

encoding bit vector is the minimum number of bits required to encode the number of enumerated values. For example, an enumeration type with five values has a 3-bit encoding vector.

The following example shows the default encoding of an enumeration type with five values.

type COLOR is (RED, GREEN, YELLOW, BLUE, VIOLET);

The enumeration values are encoded as follows.

VIOLET = “100”

The result is RED < GREEN < YELLOW < BLUE < VIOLET.

You can override the automatic enumeration encodings and specify your own enumeration encodings with the ENUM_ENCODING attribute. The interpretation of the ENUM_ENCODING attribute is specific to Foundation Express.

Several VHDL synthesis-related attributes are declared in the ATTRIBUTES package supplied with Foundation Express. For more information about this package, see the “ATTRIBUTES Package” section of the “Foundation Express Packages” chapter.

A VHDL attribute is defined by its name and type and is then declared with a value for the attributed type, as shown in the example below.

The ENUM_ENCODING attribute must be a STRING containing a series of vectors, one for each enumeration literal in the associated type. The encoding vector is specified by 0s, 1s, Ds, Us, and Zs separated by blank spaces. The meaning of these encoding vectors is described in the “Enumeration Encoding Values” section of this chapter.

The first vector in the attribute string specifies the encoding for the first enumeration literal. The second vector specifies the encoding for the second enumeration literal, and so on. The ENUM_ENCODING attribute must immediately follow the type declaration.

The following example illustrates how the default encodings from the previous example can be changed with the ENUM_ENCODING attribute.

Data Types

attribute ENUM_ENCODING: STRING; -- Attribute definition

type COLOR is (RED, GREEN, YELLOW, BLUE, VIOLET); attribute ENUM_ENCODING of

COLOR: type is "010 000 011 100 001"; -- Attribute declaration

The enumeration values are encoded as follows.

VIOLET = "001"

The result is GREEN<VIOLET<RED<YELLOW<BLUE.

Note: The interpretation of the ENUM_ENCODING attribute is specific to Foundation Express. Other VHDL tools, such as simulators, use the standard encoding (ordering).

Enumeration Encoding Values

The possible encoding values for the ENUM_ENCODING attribute follow.

•‘0’—bit value ‘0’

•‘1’—bit value ‘1’

•‘D’—don’t-care (can be either ‘0’ or ‘1’)

To use don’t care information, see the “Don’t Care Inference” section of the “Writing Circuit Descriptions” chapter

•‘U’—unknown

If ‘U’ appears in the encoding vector for an enumeration, you cannot use that enumeration literal except as an operand to the = and /= operators. You can read an enumeration literal encoded with a ‘U’ from a variable or signal, but you cannot assign it.

For synthesis, the = operator returns FALSE and the /= operator returns TRUE when either of the operands is an enumeration literal whose encoding contains ‘U.’

•‘Z’—high impedance