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VHDL Reference Guide

component AND_2 -- From a technology library port(I1, I2: in BIT;

O1: out BIT); end component;

component INVERT -- From a technology library port(I1: in BIT;

O1: out BIT); end component;

begin

U0: AND_2 port map (I1 => A, I2 => B, O1 => I); U1: INVERT port map (I1 => I, O1 => Z);

end STRUCTURAL;

The following example shows how you can define the entity NAND2 by its logical function.

architecture DATAFLOW of NAND2 is begin

Z <= A nand B; end DATAFLOW;

The following example shows another implementation of NAND2.

architecture RTL of NAND2 is begin

process(A, B) begin

if (A = ’1’) and (B = ’1’) then Z <= ’0’;

else

Z <= ’1’; end if;

end process; end RTL;

Configurations

Configurations are not currently supported by Foundation Express.

Packages

A package is a collection of declarations that more than one design can use.

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Design Descriptions

You can collect constants, data types, component declarations, and subprograms into a VHDL package that can then be used by more than one design or entity. A package must contain at least one of the following constructs.

Constants

Declare system-wide parameters, such as data-path widths.

VHDL data type declarations

Define data types used throughout a design. All entities in a design must use common interface types, such as common address bus types.

Component declarations

Specify the interfaces to entities that can be instantiated in the design.

Subprograms

Define algorithms that can be called anywhere in a design.

Packages are often sufficiently general so that you can use them in many different designs. For example, the std_logic_1164 package defines data types std_logic and std_logic_vector.

Using a Package

The use statement allows an entity to use the declarations in a package. The supported syntax of the use statement follows.

use LIBRARY_NAME.PACKAGE_NAME.ALL;

LIBRARY_NAME is the name of a VHDL library

PACKAGE_NAME is the name of the included package.

A use statement is usually the first statement in a package or entity specification source file.

Note: Foundation Express does not support different packages with the same name when they exist in different libraries. No two packages can have the same name.

VHDL Reference Guide

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VHDL Reference Guide

Package Structure

Packages have two parts; the declaration and the body.

Package declaration

Holds public information, including constant, type, and subprogram declarations

Package body

Holds private information, including local types and subprogram implementations (bodies)

Note: When a package declaration contains subprogram declarations, a corresponding package body must define the subprogram bodies.

Package Declarations

Package declarations collect information that one or more entities in a design need. This information includes data type declarations, signal declarations, subprogram declarations, and component declarations.

Note: Signals declared in packages cannot be shared across entities. If two entities both use a signal from a given package, each entity has its own copy of that signal.

Although you can declare all this information explicitly in each design entity or architecture in a system, it is often easier to declare system information in a separate package. Each design entity in the system can then use the system’s package.

The syntax of a package declaration follows.

package package_name is

{ package_declarative_item } end [ package_name ] ;

package_name is the name of this package.

A package_declarative_item is any of the following statements.

use clause (to include other packages)

type declaration

subtype declaration

constant declaration

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Xilinx Development System

Design Descriptions

signal declaration

subprogram declaration

component declaration

The following example shows some sample package declarations.

package EXAMPLE is

type BYTE is range 0 to 255;

subtype NIBBLE is BYTE range 0 to 15; constant BYTE_FF: BYTE := 255;

signal ADDEND: NIBBLE;

component

BYTE_ADDER

port(A,

B:

in BYTE;

C:

 

out BYTE;

OVERFLOW: out BOOLEAN); end component;

function MY_FUNCTION (A: in BYTE) return BYTE;

end EXAMPLE;

To use the previous example declarations, add a use statement at the beginning of your design description as follows.

use WORK.EXAMPLE.ALL; entity . . .

architecture . . .

The “Foundation Express Packages” chapter contains more examples of packages and their declarations.

Package Body

A package body includes the following.

The implementations (bodies) of subprograms declared in the package declaration.

Internal support subprograms

But designs or entities that use the package never see this information.

The syntax of a package body follows.

VHDL Reference Guide

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