Добавил:
Опубликованный материал нарушает ваши авторские права? Сообщите нам.
Вуз: Предмет: Файл:
ЛО САПР / VHDL.PDF
Скачиваний:
43
Добавлен:
17.04.2013
Размер:
5.27 Mб
Скачать

Examples

--Compute first-level Carries and second-level

--generate and propagate.

--Use first-level Generate, Propagate, and

--second-level carry.

process(GP, GG, GGC)

variable TEMP: BIT_VECTOR(3 downto 0); begin

CLA(GP(3 downto 0), GG(3 downto 0), GGC(0), TEMP, GGP(0), GGG(0));

GC(3 downto 0) <= TEMP; end process;

process(GP, GG, GGC)

variable TEMP: BIT_VECTOR(3 downto 0); begin

CLA(GP(7 downto 4), GG(7 downto 4), GGC(1), TEMP, GGP(1), GGG(1));

GC(7 downto 4) <= TEMP; end process;

--Compute second-level Carry and third-level

--Generate and Propagate

--Use second-level Generate, Propagate and Carry-in

--(CIN)

process(GGP, GGG, CIN)

variable TEMP: BIT_VECTOR(3 downto 0); begin

CLA(GGP, GGG, CIN, TEMP, GGGP, GGGG); GGC <= TEMP;

end process;

--Assign unused bits of second-level Generate and

--Propagate

GGP(3 downto 2) <= ”11”;

GGG(3 downto 2) <= ”00”;

--Compute Carry-out (COUT)

--Use third-level Generate and Propagate and

--Carry-in (CIN).

COUT <= GGGG or (GGGP and CIN); end BEHAVIOR;

Implementation

In the carry-lookahead adder implementation, procedures perform the computation of the design. The procedures can also be in the form of separate entities and used by component instantiation, producing

VHDL Reference Guide

A-49

Соседние файлы в папке ЛО САПР