- •Chapter 1
- •1.1 Motivation
- •1.2 Objective of the Specification
- •1.3 Scope of the Document
- •1.4 Document Organization
- •Chapter 2
- •Chapter 3
- •3.1 Goals for the Universal Serial Bus
- •3.2 Taxonomy of Application Space
- •3.3 Feature List
- •Chapter 4
- •4.1 USB System Description
- •4.1.1 Bus Topology
- •4.2 Physical Interface
- •4.2.1 Electrical
- •4.2.2 Mechanical
- •4.3 Power
- •4.3.1 Power Distribution
- •4.3.2 Power Management
- •4.4 Bus Protocol
- •4.5 Robustness
- •4.5.1 Error Detection
- •4.5.2 Error Handling
- •4.6 System Configuration
- •4.6.1 Attachment of USB Devices
- •4.6.2 Removal of USB Devices
- •4.6.3 Bus Enumeration
- •4.7 Data Flow Types
- •4.7.1 Control Transfers
- •4.7.2 Bulk Transfers
- •4.7.3 Interrupt Transfers
- •4.7.4 Isochronous Transfers
- •4.7.5 Allocating USB Bandwidth
- •4.8 USB Devices
- •4.8.1 Device Characterizations
- •4.8.2 Device Descriptions
- •4.9 USB Host: Hardware and Software
- •4.10 Architectural Extensions
- •Chapter 5
- •5.1 Implementer Viewpoints
- •5.2 Bus Topology
- •5.2.1 USB Host
- •5.2.2 USB Devices
- •5.2.3 Physical Bus Topology
- •5.2.4 Logical Bus Topology
- •5.2.5 Client Software-to-function Relationship
- •5.3 USB Communication Flow
- •5.3.1 Device Endpoints
- •5.3.2 Pipes
- •5.4 Transfer Types
- •5.5 Control Transfers
- •5.5.1 Control Transfer Data Format
- •5.5.2 Control Transfer Direction
- •5.5.3 Control Transfer Packet Size Constraints
- •5.5.4 Control Transfer Bus Access Constraints
- •5.5.5 Control Transfer Data Sequences
- •5.6 Isochronous Transfers
- •5.6.1 Isochronous Transfer Data Format
- •5.6.2 Isochronous Transfer Direction
- •5.6.3 Isochronous Transfer Packet Size Constraints
- •5.6.4 Isochronous Transfer Bus Access Constraints
- •5.6.5 Isochronous Transfer Data Sequences
- •5.7 Interrupt Transfers
- •5.7.1 Interrupt Transfer Data Format
- •5.7.2 Interrupt Transfer Direction
- •5.7.3 Interrupt Transfer Packet Size Constraints
- •5.7.4 Interrupt Transfer Bus Access Constraints
- •5.7.5 Interrupt Transfer Data Sequences
- •5.8 Bulk Transfers
- •5.8.1 Bulk Transfer Data Format
- •5.8.2 Bulk Transfer Direction
- •5.8.3 Bulk Transfer Packet Size Constraints
- •5.8.4 Bulk Transfer Bus Access Constraints
- •5.8.5 Bulk Transfer Data Sequences
- •5.9 Bus Access for Transfers
- •5.9.1 Transfer Management
- •5.9.2 Transaction Tracking
- •5.9.3 Calculating Bus Transaction Times
- •5.9.4 Calculating Buffer Sizes in Functions and Software
- •5.9.5 Bus Bandwidth Reclamation
- •5.10 Special Considerations for Isochronous Transfers
- •5.10.1 Example Non-USB Isochronous Application
- •5.10.2 USB Clock Model
- •5.10.3 Clock Synchronization
- •5.10.4 Isochronous Devices
- •5.10.5 Data Prebuffering
- •5.10.6 SOF Tracking
- •5.10.7 Error Handling
- •5.10.8 Buffering for Rate Matching
- •Chapter 6
- •6.1 Architectural Overview
- •6.3 Cable
- •6.4 Cable Assembly
- •6.4.1 Detachable Cable Assemblies
- •6.4.3 Low-speed Captive Cable Assemblies
- •6.4.4 Prohibited Cable Assemblies
- •6.5.1 USB Icon Location
- •6.5.2 USB Connector Termination Data
- •6.5.3 Series “A” and Series “B” Receptacles
- •6.5.4 Series “A” and Series “B” Plugs
- •6.6.1 Description
- •6.6.2 Construction
- •6.6.3 Electrical Characteristics
- •6.6.4 Cable Environmental Characteristics
- •6.6.5 Listing
- •6.7 Electrical, Mechanical and Environmental Compliance Standards
- •6.7.1 Applicable Documents
- •6.8 USB Grounding
- •Chapter 7
- •7.1 Signaling
- •7.1.1 USB Driver Characteristics
- •7.1.2 Data Signal Rise and Fall
- •7.1.3 Cable Skew
- •7.1.4 Receiver Characteristics
- •7.1.5 Device Speed Identification
- •7.1.6 Input Characteristics
- •7.1.7 Signaling Levels
- •7.1.8 Data Encoding/Decoding
- •7.1.9 Bit Stuffing
- •7.1.10 Sync Pattern
- •7.1.11 Data Signaling Rate
- •7.1.12 Frame Interval and Frame Interval Adjustment
- •7.1.13 Data Source Signaling
- •7.1.14 Hub Signaling Timings
- •7.1.15 Receiver Data Jitter
- •7.1.16 Cable Delay
- •7.1.17 Cable Attenuation
- •7.1.18 Bus Turn-around Time and Inter-packet Delay
- •7.1.19 Maximum End-to-end Signal Delay
- •7.2 Power Distribution
- •7.2.1 Classes of Devices
- •7.2.2 Voltage Drop Budget
- •7.2.3 Power Control During Suspend/Resume
- •7.2.4 Dynamic Attach and Detach
- •7.3 Physical Layer
- •7.3.1 Regulatory Requirements
- •7.3.2 Bus Timing/Electrical Characteristics
- •7.3.3 Timing Waveforms
- •Chapter 8
- •8.1 Bit Ordering
- •8.2 SYNC Field
- •8.3 Packet Field Formats
- •8.3.1 Packet Identifier Field
- •8.3.2 Address Fields
- •8.3.3 Frame Number Field
- •8.3.4 Data Field
- •8.3.5 Cyclic Redundancy Checks
- •8.4 Packet Formats
- •8.4.1 Token Packets
- •8.4.2 Start-of-Frame Packets
- •8.4.3 Data Packets
- •8.4.4 Handshake Packets
- •8.4.5 Handshake Responses
- •8.5 Transaction Formats
- •8.5.1 Bulk Transactions
- •8.5.2 Control Transfers
- •8.5.3 Interrupt Transactions
- •8.5.4 Isochronous Transactions
- •8.6 Data Toggle Synchronization and Retry
- •8.6.1 Initialization via SETUP Token
- •8.6.2 Successful Data Transactions
- •8.6.3 Data Corrupted or Not Accepted
- •8.6.4 Corrupted ACK Handshake
- •8.6.5 Low-speed Transactions
- •8.7 Error Detection and Recovery
- •8.7.1 Packet Error Categories
- •8.7.2 Bus Turn-around Timing
- •8.7.3 False EOPs
- •8.7.4 Babble and Loss of Activity Recovery
- •Chapter 9
- •9.1 USB Device States
- •9.1.1 Visible Device States
- •9.1.2 Bus Enumeration
- •9.2 Generic USB Device Operations
- •9.2.1 Dynamic Attachment and Removal
- •9.2.2 Address Assignment
- •9.2.3 Configuration
- •9.2.4 Data Transfer
- •9.2.5 Power Management
- •9.2.6 Request Processing
- •9.2.7 Request Error
- •9.3 USB Device Requests
- •9.3.1 bmRequestType
- •9.3.2 bRequest
- •9.3.3 wValue
- •9.3.4 wIndex
- •9.3.5 wLength
- •9.4 Standard Device Requests
- •9.4.1 Clear Feature
- •9.4.2 Get Configuration
- •9.4.3 Get Descriptor
- •9.4.4 Get Interface
- •9.4.5 Get Status
- •9.4.6 Set Address
- •9.4.7 Set Configuration
- •9.4.8 Set Descriptor
- •9.4.9 Set Feature
- •9.4.10 Set Interface
- •9.4.11 Synch Frame
- •9.5 Descriptors
- •9.6 Standard USB Descriptor Definitions
- •9.6.1 Device
- •9.6.2 Configuration
- •9.6.3 Interface
- •9.6.4 Endpoint
- •9.6.5 String
- •9.7 Device Class Definitions
- •9.7.1 Descriptors
- •9.7.2 Interface(s) and Endpoint Usage
- •9.7.3 Requests
- •Chapter 10
- •10.1 Overview of the USB Host
- •10.1.1 Overview
- •10.1.2 Control Mechanisms
- •10.1.3 Data Flow
- •10.1.4 Collecting Status and Activity Statistics
- •10.1.5 Electrical Interface Considerations
- •10.2 Host Controller Requirements
- •10.2.1 State Handling
- •10.2.2 Serializer/Deserializer
- •10.2.3 Frame Generation
- •10.2.4 Data Processing
- •10.2.5 Protocol Engine
- •10.2.6 Transmission Error Handling
- •10.2.7 Remote Wakeup
- •10.2.8 Root Hub
- •10.2.9 Host System Interface
- •10.3 Overview of Software Mechanisms
- •10.3.1 Device Configuration
- •10.3.2 Resource Management
- •10.3.3 Data Transfers
- •10.3.4 Common Data Definitions
- •10.4 Host Controller Driver
- •10.5 Universal Serial Bus Driver
- •10.5.1 USBD Overview
- •10.5.2 USBD Command Mechanism Requirements
- •10.5.3 USBD Pipe Mechanisms
- •10.5.4 Managing the USB via the USBD Mechanisms
- •10.5.5 Passing USB Preboot Control to the Operating System
- •10.6 Operating System Environment Guides
- •Chapter 11
- •11.1 Overview
- •11.1.1 Hub Architecture
- •11.1.2 Hub Connectivity
- •11.2 Hub Frame Timer
- •11.2.1 Frame Timer Synchronization
- •11.2.2 EOF1 and EOF2 Timing Points
- •11.3 Host Behavior at End-of-Frame
- •11.3.1 Latest Host Packet
- •11.3.2 Packet Nullification
- •11.3.3 Transaction Completion Prediction
- •11.4 Internal Port
- •11.4.1 Inactive
- •11.4.2 Suspend Delay
- •11.4.3 Full Suspend (Fsus)
- •11.4.4 Generate Resume (GResume)
- •11.5 Downstream Ports
- •11.5.1 Downstream Port State Descriptions
- •11.6 Upstream Port
- •11.6.1 Receiver
- •11.6.2 Transmitter
- •11.7 Hub Repeater
- •11.7.1 Wait for Start of Packet from Upstream Port (WFSOPFU)
- •11.7.2 Wait for End of Packet from Upstream Port (WFEOPFU)
- •11.7.3 Wait for Start of Packet (WFSOP)
- •11.7.4 Wait for End of Packet (WFEOP)
- •11.8 Bus State Evaluation
- •11.8.1 Port Error
- •11.8.2 Speed Detection
- •11.8.3 Collision
- •11.9 Suspend and Resume
- •11.10 Hub Reset Behavior
- •11.10.1 Hub Receiving Reset on Upstream Port
- •11.11 Hub Port Power Control
- •11.11.1 Multiple Gangs
- •11.12 Hub I/O Buffer Requirements
- •11.12.1 Pull-up and Pull-down Resistors
- •11.12.2 Edge Rate Control
- •11.13 Hub Controller
- •11.13.1 Endpoint Organization
- •11.13.2 Hub Information Architecture and Operation
- •11.13.3 Port Change Information Processing
- •11.13.4 Hub and Port Status Change Bitmap
- •11.13.5 Over-current Reporting and Recovery
- •11.14 Hub Configuration
- •11.15 Descriptors
- •11.15.1 Standard Descriptors
- •11.15.2 Class-specific Descriptors
- •11.16 Requests
- •11.16.1 Standard Requests
- •11.16.2 Class-specific Requests
- •Index
Universal Serial Bus Specification Revision 1.1
to ensure that the inductive flyback on the open end of the cable does not cause the voltage on the device end to reverse polarity. A minimum of 1.0 F is recommended for bypass across VBUS.
7.3 Physical Layer
The physical layer specifications are described in the following subsections.
141
Universal Serial Bus Specification Revision 1.1
7.3.1 Regulatory Requirements
All USB devices should be designed to meet the applicable regulatory requirements.
7.3.2 Bus Timing/Electrical Characteristics
Table 7-5. DC Electrical Characteristics
Parameter |
Symbol |
Conditions |
Min. |
Max. |
Units |
|
|
|
|
|
|
Supply Voltage: |
|
|
|
|
|
|
|
|
|
|
|
High-power Port |
VBUS |
Note 2, Section 7.2.1 |
4.75 |
5.25 |
V |
|
|
|
|
|
|
Low-power Port |
VBUS |
Note 2, Section 7.2.1 |
4.40 |
5.25 |
V |
|
|
|
|
|
|
Supply Current: |
|
|
|
|
|
|
|
|
|
|
|
High-power Hub Port (out) |
ICCPRT |
Section 7.2.1 |
500 |
|
mA |
|
|
|
|
|
|
Low-power Hub Port (out) |
ICCUPT |
Section 7.2.1 |
100 |
|
mA |
|
|
|
|
|
|
High-power Function (in) |
ICCHPF |
Section 7.2.1 |
|
500 |
mA |
|
|
|
|
|
|
Low-power Function (in) |
ICCLPF |
Section 7.2.1 |
|
100 |
mA |
|
|
|
|
|
|
Unconfigured Function/Hub (in) |
ICCINIT |
Section 7.2.1.4 |
|
100 |
mA |
|
|
|
|
|
|
Suspended High-power Device |
ICCSH |
Section 7.2.3 ; Note 15 |
|
2.5 |
mA |
|
|
|
|
|
|
Suspended Low-power Device |
ICCSL |
Section 7.2.3 |
|
500 |
A |
|
|
|
|
|
|
Input Levels: |
|
|
|
|
|
|
|
|
|
|
|
High (driven) |
VIH |
Note 4, Section 7.1.4 |
2.0 |
|
V |
|
|
|
|
|
|
High (floating) |
VIHZ |
Note 4, Section 7.1.4 |
2.7 |
3.6 |
V |
|
|
|
|
|
|
Low |
VIL |
Note 4, Section 7.1.4 |
|
0.8 |
V |
|
|
|
|
|
|
Differential Input Sensitivity |
VDI |
|(D+)-(D-)|; |
0.2 |
|
V |
|
|
Figure 7-9; Note 4 |
|
|
|
|
|
|
|
|
|
Differential Common Mode |
VCM |
Includes VDI range; |
0.8 |
2.5 |
V |
Range |
|
Figure 7-9; Note 4 |
|
|
|
|
|
|
|
|
|
Output Levels: |
|
|
|
|
|
|
|
|
|
|
|
Low |
VOL |
Note 4, 5, Section 7.1.1 |
0.0 |
0.3 |
V |
|
|
|
|
|
|
High (Driven) |
VOH |
Note 4, 6, Section 7.1.1 |
2.8 |
3.6 |
V |
|
|
|
|
|
|
Output Signal Crossover |
VCRS |
Measured as in Figure |
1.3 |
2.0 |
V |
Voltage |
|
7-6; Note 10 |
|
|
|
|
|
|
|
|
|
Decoupling Capacitance: |
|
|
|
|
|
|
|
|
|
|
|
Downstream Port Bypass |
CHPB |
VBUS to GND, Section |
120 |
|
F |
Capacitance (per hub) |
|
7.2.4.1 |
|
|
|
|
|
|
|
|
|
Upstream Port Bypass |
CRPB |
VBUS to GND; Note 9, |
1.0 |
10.0 |
F |
Capacitance |
|
Section 7.2.4.1 |
|
|
|
|
|
|
|
|
|
142
Universal Serial Bus Specification Revision 1.1
Table 7-5. DC Electrical Characteristics (Continued)
Parameter |
Symbol |
Conditions |
Min. |
Max. |
Units |
|
|
|
|
|
|
Input Capacitance: |
|
|
|
|
|
|
|
|
|
|
|
Downstream Port |
CIND |
Note 2; Section 7.1.6 |
|
150 |
pF |
|
|
|
|
|
|
Upstream Port (w/o cable) |
CINUB |
Note 3; Section 7.1.6 |
|
100 |
pF |
|
|
|
|
|
|
Transceiver edge rate control |
CEDGE |
Section 7.1.6 |
|
75 |
pF |
capacitance |
|
|
|
|
|
|
|
|
|
|
|
Terminations: |
|
|
|
|
|
|
|
|
|
|
|
Bus Pull-up Resistor on |
RPU |
1.5k 5% |
1.425 |
1.575 |
k |
Upstream Port |
|
Section 7.1.5 |
|
|
|
|
|
|
|
|
|
Bus Pull-down Resistor on |
RPD |
15k 5% |
14.25 |
15.75 |
k |
Downstream Port |
|
Section 7.1.5 |
|
|
|
|
|
|
|
|
|
Input impedance exclusive of |
ZINP |
Section 7.1.6 |
300 |
|
k |
pullup/pulldown |
|
|
|
|
|
|
|
|
|
|
|
Termination voltage for |
VTERM |
Section 7.1.5 |
3.0 |
3.6 |
V |
upstream port pullup (RPU) |
|
|
|
|
|
|
|
|
|
|
|
143
Universal Serial Bus Specification Revision 1.1
Table 7-6. Full-speed Source Electrical Characteristics
Parameter |
Symbol |
Conditions |
Min. |
Max. |
Units |
|
|
|
|
|
|
Driver Characteristics: |
|
|
|
|
|
|
|
|
|
|
|
Rise Time |
TFR |
Figure 7-6; Figure 7-7 |
4 |
20 |
ns |
|
|
|
|
|
|
Fall Time |
TFF |
Figure 7-6; Figure 7-7 |
4 |
20 |
ns |
|
|
|
|
|
|
Differential Rise and Fall Time |
TFRFM |
(TFR/TFF) Note 10, Section |
90 |
111.11 |
% |
Matching |
|
7.1.2 |
|
|
|
|
|
|
|
|
|
Driver Output Resistance |
ZDRV |
Section 7.1.1.1 |
28 |
44 |
|
|
|
|
|
|
|
Clock Timings: |
|
|
|
|
|
|
|
|
|
|
|
Full-speed Data Rate |
TFDRATE |
Average bit rate, Section |
11.9700 |
12.0300 |
Mb/s |
|
|
7.1.11 |
|
|
|
|
|
|
|
|
|
Frame Interval |
TFRAME |
Section 7.1.12 |
0.9995 |
1.0005 |
ms |
|
|
|
|
|
|
Consecutive Frame Interval |
TRFI |
No clock adjustment |
|
42 |
ns |
Jitter |
|
|
|
|
|
|
|
|
|
|
|
Consecutive Frame Interval |
TRFIADJ |
With clock adjustment |
|
126 |
ns |
Jitter |
|
|
|
|
|
|
|
|
|
|
|
Full-speed Data Timings: |
|
|
|
|
|
|
|
|
|
|
|
Source Jitter Total (including |
|
Note 7, 8, 12, 10; |
|
|
|
frequency tolerance): |
|
Measured as in Figure |
|
|
|
To Next Transition |
TDJ1 |
7-39; |
-3.5 |
3.5 |
ns |
|
|||||
For Paired Transitions |
TDJ2 |
|
-4 |
4 |
ns |
|
|
|
|
|
|
Source Jitter for Differential |
TFDEOP |
Note 8; Figure 7-40; |
-2 |
5 |
ns |
Transition to SE0 Transition |
|
Note 11 |
|
|
|
|
|
|
|
|
|
Receiver Jitter: |
|
Note 8; Figure 7-41 |
|
|
|
To Next Transition |
TJR1 |
|
-18.5 |
18.5 |
ns |
For Paired Transitions |
TJR2 |
|
-9 |
9 |
ns |
|
|
|
|
|
|
Source SE0 interval of EOP |
TFEOPT |
Figure 7-40 |
160 |
175 |
ns |
|
|
|
|
|
|
Receiver SE0 interval of EOP |
TFEOPR |
Note 13; Section 7.1.13.2; |
82 |
|
ns |
|
|
Figure 7-40 |
|
|
|
|
|
|
|
|
|
Width of SE0 interval during |
TFST |
Section 7.1.4 |
|
14 |
ns |
differential transition |
|
|
|
|
|
|
|
|
|
|
|
144
Universal Serial Bus Specification Revision 1.1
Table 7-7. Low-speed Source Electrical Characteristics
Parameter |
Symbol |
Conditions |
Min. |
Max. |
Units |
|
|
|
|
|
|
Driver Characteristics: |
|
|
|
|
|
|
|
|
|
|
|
Transition Time: |
|
|
|
|
|
Rise Time |
TLR |
Measured as in Figure 7-6 |
75 |
300 |
ns |
Fall Time |
TLF |
|
75 |
300 |
ns |
|
|
|
|
|
|
Rise and Fall Time Matching |
TLRFM |
(TLR/TLF) Note 10 |
80 |
125 |
% |
|
|
|
|
|
|
Upstream Port |
CLINUA |
Note 1; Section 7.1.6 |
200 |
450 |
pF |
(w/cable, low-speed only) |
|
|
|
|
|
|
|
|
|
|
|
Clock Timings: |
|
|
|
|
|
|
|
|
|
|
|
Low-speed Data Rate |
TLDRATE |
Section 7.1.11 |
1.4775 |
1.5225 |
Mb/s |
|
|
|
|
|
|
Low-speed Data Timings: |
|
|
|
|
|
|
|
|
|
|
|
Upstream port source Jitter |
|
Note 7, 8; Figure 7-39 |
|
|
|
Total (including frequency |
TUDJ1 |
|
-95 |
95 |
ns |
tolerance): |
|
||||
TUDJ2 |
|
-150 |
150 |
ns |
|
|
|
||||
To Next Transition |
|
|
|
|
|
For Paired Transitions |
|
|
|
|
|
|
|
|
|
|
|
Upstream port source Jitter for |
TLDEOP |
Note 8; Figure 7-40; |
-40 |
100 |
ns |
Differential Transition to SE0 |
|
Note 11 |
|
|
|
Transition |
|
|
|
|
|
|
|
|
|
|
|
Upstream port differential |
|
Note 8; Figure 7-41 |
|
|
|
Receiver Jitter: |
TDJR1 |
|
-75 |
75 |
ns |
|
|
||||
To Next Transition |
TDJR2 |
|
-45 |
45 |
ns |
For Paired Transitions |
|
|
|
|
|
|
|
|
|
|
|
Downstream port source Jitter |
|
Note 7, 8; Figure 7-39 |
|
|
|
Total (including frequency |
TDDJ1 |
|
-25 |
25 |
ns |
tolerance): |
|
||||
TDDJ2 |
|
-14 |
14 |
ns |
|
|
|
||||
To Next Transition |
|
|
|
|
|
For Paired Transitions |
|
|
|
|
|
Downstream port source Jitter |
|
Note 8; Figure 7-40; |
|
|
ns |
for Differential Transition to SE0 |
|
Note 11 |
|
|
|
Transition |
|
|
|
|
|
|
|
|
|
|
|
Downstream port Differential |
|
Note 8; Figure 7-40 |
|
|
|
Receiver Jitter: |
TUJR1 |
|
-152 |
152 |
ns |
To Next Transition |
|
||||
TUJR2 |
|
-200 |
200 |
ns |
|
For Paired Transitions |
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
Source SE0 interval of EOP |
TLEOPT |
Figure 7-40 |
1.25 |
1.50 |
µs |
|
|
|
|
|
|
Receiver SE0 interval of EOP |
TLEOPR |
Note 13; Section 7.1.13.2; |
670 |
|
ns |
|
|
Figure 7-40 |
|
|
|
|
|
|
|
|
|
Width of SE0 interval during |
TLST |
Section 7.1.4 |
|
210 |
ns |
differential transition |
|
|
|
|
|
|
|
|
|
|
|
145
Universal Serial Bus Specification Revision 1.1
Table 7-8. Hub/Repeater Electrical Characteristics
Parameter |
Symbol |
Conditions |
Min. |
Max. |
Units |
|
|
|
|
|
|
Full-speed Hub Characteristics (as measured at connectors):
Driver Characteristics: |
|
Upstream port and |
|
|
|
(Refer to Table 7-6) |
|
downstream ports |
|
|
|
|
|
configured as full-speed |
|
|
|
|
|
|
|
|
|
Hub Differential Data Delay: |
|
Note 7, 8 |
|
|
|
(with cable) |
THDD1 |
Figure 7-42A |
|
70 |
ns |
(without cable) |
THDD2 |
Figure 7-42B |
|
44 |
ns |
|
|
|
|
|
|
Hub Differential Driver Jitter: |
|
Note 7, 8; Figure 7-42, |
|
|
|
(including cable) |
|
Section 7.1.14 |
|
|
|
To Next Transition |
THDJ1 |
|
-3 |
3 |
ns |
For Paired Transitions |
THDJ2 |
|
-1 |
1 |
ns |
|
|
|
|
|
|
Data Bit Width Distortion after SOP |
TFSOP |
Note 8; Figure 7-42 |
-5 |
5 |
ns |
|
|
|
|
|
|
Hub EOP Delay Relative to THDD |
TFEOPD |
Note 8; Figure 7-43 |
0 |
15 |
ns |
|
|
|
|
|
|
Hub EOP Output Width Skew |
TFHESK |
Note 8; Figure 7-43 |
-15 |
15 |
ns |
|
|
|
|
|
|
Low-speed Hub Characteristics (as measured at connectors):
Driver Characteristics: |
|
Downstream ports |
|
|
|
(Refer to Table 7-7) |
|
configured as low-speed |
|
|
|
|
|
|
|
|
|
Hub Differential Data Delay |
TLHDD |
Note 7, 8; Figure 7-42 |
|
300 |
ns |
|
|
|
|
|
|
Hub Differential Driver Jitter |
|
Note 7, 8; Figure 7-42 |
|
|
|
(including cable): |
|
|
|
|
|
Downstream port : |
|
|
|
|
|
To Next Transition |
TLDHJ1 |
|
-45 |
45 |
ns |
For Paired Transitions |
TLDHJ2 |
|
-15 |
15 |
ns |
Upstream port: |
|
|
|
|
|
To Next Transition |
TLUHJ1 |
|
-45 |
45 |
ns |
For Paired Transitions |
TLUHJ2 |
|
-45 |
45 |
ns |
|
|
|
|
|
|
Data Bit Width Distortion after SOP |
TLSOP |
Note 8; Figure 7-42 |
-60 |
60 |
ns |
|
|
|
|
|
|
Hub EOP Delay Relative to THDD |
TLEOPD |
Note 8; Figure 7-43 |
0 |
200 |
ns |
|
|
|
|
|
|
Hub EOP Output Width Skew |
TLHESK |
Note 8; Figure 7-43 |
-300 |
+300 |
ns |
|
|
|
|
|
|
146
Universal Serial Bus Specification Revision 1.1 |
|
|
|||
|
Table 7-9. Cable Characteristics (Note 14) |
|
|
||
|
|
|
|
|
|
Parameter |
Symbol |
Conditions |
Min |
Max |
Units |
|
|
|
|
|
|
VBUS Voltage drop for |
VBUSD |
Section 7.2.2 |
|
125 |
mV |
detachable cables |
|
|
|
|
|
|
|
|
|
|
|
GND Voltage drop (for all |
VGNDD |
Section 7.2.2 |
|
125 |
mV |
cables) |
|
|
|
|
|
|
|
|
|
|
|
Differential Cable Impedance |
ZO |
(90 15%); |
76.5 |
103.5 |
|
(full-speed) |
|
|
|
|
|
|
|
|
|
|
|
Cable Delay (one way) |
|
Section 7.1.16 |
|
|
|
Full-speed |
TFSCBL |
|
|
26 |
ns |
Low-speed |
TLSCBL |
|
|
18 |
ns |
|
|
|
|
|
|
Cable Skew |
TSKEW |
Section 7.1.3 |
|
400 |
ps |
|
|
|
|
|
|
Unmated Contact Capacitance |
CUC |
Section 6.7 |
|
2 |
pF |
|
|
|
|
|
|
Note 1: Measured at A plug
Note 2: Measured at A receptacle
Note 3: Measured at B receptacle
Note 4: Measured at A or B connector
Note 5: Measured with RL of 1.425k to 3.6V
Note 6: Measured with RL of 14.25k to GND
Note 7: Timing difference between the differential data signals
Note 8: Measured at crossover point of differential data signals
Note 9: The maximum load specification is the maximum effective capacitive load allowed that meets the target VBUS drop of 330mV
Note 10: Excluding the first transition from the Idle state
Note 11: The two transitions should be a (nominal) bit time apart
Note 12: For both transitions of differential signaling
Note 13: Must accept as valid EOP
Note 14: Single-ended capacitance of D+ or D- is the capacitance of D+/D- to all other conductors and, if present, shield in the cable. I.e., to measure the single-ended capacitance of D+, short D-, VBUS, GND and the shield line together and measure the capacitance of D+ to the other conductors.
Note 15: For high power devices (non-hubs) when enabled for remote wakeup
147
Universal Serial Bus Specification Revision 1.1
Table 7-10. Hub Event Timings
Event Description |
Symbol |
Conditions |
Min |
Max |
Unit |
|
|
|
|
|
|
Time to detect a downstream port |
TDCNN |
Section 11.5 and Section |
|
|
|
connect event |
|
7.1.7.1 |
|
|
|
Awake Hub |
|
|
2.5 |
2000 |
s |
Suspended Hub |
|
|
2.5 |
12000 |
s |
|
|
|
|
|
|
Time to detect a disconnect event |
TDDIS |
Section 7.1.7.1 |
|
|
|
at a downstream port: |
|
|
|
|
|
Awake Hub |
|
|
2 |
2.5 |
s |
Suspended Hub |
|
|
2 |
10000.0 |
s |
|
|
|
|
|
|
Duration of driving resume to a |
TDRSMDN |
Nominal; Section 7.1.7.5 |
20 |
|
ms |
downstream port; Only from a |
|
and Section 11.5 |
|
|
|
controlling hub |
|
|
|
|
|
|
|
|
|
|
|
Time from detecting downstream |
TURSM |
Section 7.1.7.5 |
|
100 |
µs |
resume to rebroadcast. |
|
|
|
|
|
|
|
|
|
|
|
Duration of driving reset to a |
TDRST |
Only for a |
10 |
20 |
ms |
downstream port |
|
SetPortFeature |
|
|
|
|
|
(PORT_RESET) request; |
|
|
|
|
|
Section 7.1.7.3 and |
|
|
|
|
|
Section 11.5 |
|
|
|
|
|
|
|
|
|
Overall duration of driving reset to |
TDRSTR |
only for root hubs; |
50 |
|
ms |
downstream port, root hub |
|
Section 7.1.7.3 |
|
|
|
|
|
|
|
|
|
Maximum interval between reset |
TRHRSI |
only for root hubs; each |
|
3 |
ms |
segments used to create TDRSTR |
|
reset pulse must be of |
|
|
|
|
|
length TDRST; Section |
|
|
|
|
|
7.1.7.3 |
|
|
|
|
|
|
|
|
|
Time to evaluate device speed |
TDSPDEV |
Optional |
2.5 |
1000 |
s |
after reset |
|
Section 11.8.2 |
|
|
|
|
|
|
|
|
|
Time to detect a long K from |
TURLK |
Section 11.6.1 |
2.5 |
100 |
s |
upstream |
|
|
|
|
|
|
|
|
|
|
|
Time to detect a long SE0 from |
TURLSE0 |
Section 11.6.1 |
2.5 |
10000 |
s |
upstream |
|
|
|
|
|
|
|
|
|
|
|
Duration of repeating SE0 |
TURPSE0 |
Section 11.6.2 |
|
23 |
FS bit |
upstream |
|
|
|
|
times |
|
|
|
|
|
|
Duration of sending SE0 upstream |
TUDEOP |
Optional |
|
2 |
FS bit |
after EOF1 |
|
Section 11.6.2 |
|
|
times |
|
|
|
|
|
|
148
Universal Serial Bus Specification Revision 1.1
Table 7-11. Device Event Timings
Parameter |
Symbol |
Conditions |
Min |
Max |
Units |
|
|
|
|
|
|
Time from internal power good to |
TSIGATT |
Figure 7-19 |
|
100 |
ms |
device pulling D+/D- beyond VIHZ |
|
|
|
|
|
(min) (signaling attach) |
|
|
|
|
|
|
|
|
|
|
|
Debounce interval provided by |
TATTDB |
Figure 7-19 |
|
100 |
ms |
USB system software after attach |
|
|
|
|
|
|
|
|
|
|
|
Maximum time a device can draw |
T2SUSP |
Section 7.1.7.4 |
|
10 |
ms |
power >suspend power when bus |
|
|
|
|
|
is continuously in idle state |
|
|
|
|
|
|
|
|
|
|
|
Maximum duration of suspend |
TSUSAVGI |
Section 7.2.3 |
|
1 |
s |
averaging interval |
|
|
|
|
|
|
|
|
|
|
|
Period of idle bus before device |
TWTRSM |
Device must be |
5 |
|
ms |
can initiate resume |
|
remote-wakeup |
|
|
|
|
|
enabled. Section |
|
|
|
|
|
7.1.7.5 |
|
|
|
|
|
|
|
|
|
Duration of driving resume |
TDRSMUP |
Section 7.1.7.5 |
1 |
15 |
ms |
upstream |
|
|
|
|
|
|
|
|
|
|
|
Resume Recovery Time |
TRSMRCY |
Provided by USB |
10 |
|
ms |
|
|
System Software; |
|
|
|
|
|
Section 7.1.7.5 |
|
|
|
|
|
|
|
|
|
Time to detect a reset from |
TDETRST |
Section 7.1.7.3 |
2.5 |
10000 |
s |
upstream |
|
|
|
|
|
|
|
|
|
|
|
Reset Recovery Time |
TRSTRCY |
Section 7.1.7.3 |
|
10 |
ms |
|
|
|
|
|
|
Inter-packet Delay |
TIPD |
Section 7.1.18 |
2 |
|
bit |
|
|
|
|
|
times |
|
|
|
|
|
|
Inter-packet delay for device |
TRSPIPD1 |
Section 7.1.18 |
|
6.5 |
bit |
response w/detachable cable |
|
|
|
|
times |
|
|
|
|
|
|
Inter-packet delay for device |
TRSPIPD2 |
Section 7.1.18 |
|
7.5 |
bit |
response w/captive cable |
|
|
|
|
times |
|
|
|
|
|
|
SetAddress() Completion Time |
TDSETADDR |
Section 9.2.6.3 |
|
50 |
ms |
|
|
|
|
|
|
Time to complete standard |
TDRQCMPLTND |
Section 9.2.6.4 |
|
50 |
ms |
request with no data |
|
|
|
|
|
|
|
|
|
|
|
149
Universal Serial Bus Specification Revision 1.1
Table 7-11. Device Event Timings (Continued)
Parameter |
Symbol |
Conditions |
Min |
Max |
Units |
|
|
|
|
|
|
Time to deliver first and |
TDRETDATA1 |
Section 9.2.6.4 |
|
500 |
ms |
subsequent (except last) data for |
|
|
|
|
|
standard request |
|
|
|
|
|
|
|
|
|
|
|
Time to deliver last data for |
TDRETDATAN |
Section 9.2.6.4 |
|
50 |
ms |
standard request |
|
|
|
|
|
|
|
|
|
|
|
150