Chapter 1: Clock Resources

Examples of High-Speed I/O Clock Network Connections

The examples in this section illustrate how the global clock buffers, I/O clock buffers, and I/O tile can be used together for high-speed interfaces.

The example in Figure 1-14 shows the simplest implementation where an input clock is used to clock the ISERDES2. The BUFIO2 provides the FPGA logic clock as well as the strobe signals used by ISERDES2. Serial data is clocked using IOCLK on the I/O clock network. Parallel data is clocked out in the FPGA clock domain using the DIVCLK output and the synchronous SERDESSTROBE signal.

Figure 1-14: Example 1: BUFIO2 Driving ISERDES2, DATA_RATE = SDR

In DDR applications where serialized data is clocked in on both the rising and falling edges of the input clock, a second inverted clock is required to drive CLK1 as shown Figure 1-15. Because data is clocked in on both edges of the IOCLK, DIVCLK is divided by a DIVIDE/2 by setting USE_DOUBLER = TRUE.

Figure 1-15: Example 2: BUFIO2 Driving ISERDES2, DATA_RATE = DDR

Chapter 1: Clock Resources

Designs with high-speed source synchronous outputs do not require exact timing delays from the GCLK input to the I/O clock domain. When timing alignment is not required, the PLL can use a dedicated feedback from CLKFBOUT to CLKFBIN without the use of any clock buffers (Figure 1-17).

BUFG

CLK_FEEDBACK = CLKFBOUT

UG382_c1_11_120809

Figure 1-17: Example 4: Basic PLL OSERDES2 (SDR)

In designs where DCM_SP performance is adequate, DCM_SP can be used to drive IOLOGIC (IDDR2) using up to three BUFG clock buffers. To match the input routing delays, either CLK0 or CLK2X must be used to drive the BUFIO2FB as shown in Figure 1-18.

To maintain the best duty-cycle performance using the DCM, use separate DCM clock outputs to drive C0 and C1. Each DCM output drives a separate global buffer. While possible using the BUFG to invert one phase locally within the I/O tile, it is not recommended as locally inverting one of the clocks inserts duty-cycle distortion.

Figure 1-18: Example 5: DCM Deskewed to the Inputs

When using GTP transceivers, GTP reference clocks contain dedicated routing connections to BUFIO2 that can be used to connect to the Clock Management Tiles (CMT).

Chapter 1: Clock Resources

Example 7 in Figure 1-20 shows a single lane PCI Express design where the input frequency and feedback frequency are different. Because the input frequency and the feedback frequency do not match, additional analysis of the PLL settings is required. In this example, GTPCLKOUT0[0] is a 100 MHz clock. To create a feedback clock frequency that meets both the GTP_DUAL and PLL requirements, a 250 MHz feedback clock is selected by setting TXDATAWIDTH0[0] = 2.

To allow for more flexibility in matching the Phase-Frequency Detector (PFD) frequencies, the PLL is setup to use CLK_FEEDBACK = CLKOUT0. The PFD operates at 50 MHz and, using the given settings, the VCO is 500 MHz.

Additional instructions for selecting PLL settings are described in Chapter 3, PhaseLocked Loops. See UG386, Spartan-6 FPGA GTP Transceivers User Guide for more information.