Chapter 1: Clock Resources

to the DCM/PLL in the top half of the device. Similarly, BUFIO2 buffers connected to the bottom half of the device (BUFIO2 clocking regions BL, BR, LB, and RB) are connected to the DCM/PLL in the bottom half of the device. See Figure 1-9, Figure 1-10, and Figure 1-11.

Clocking Structure Guidelines

The advanced features of the Spartan-6 FPGA SelectIO logic can require different clocking structures to support a range of different SelectIO solutions. This section outlines the recommended clocking solutions for optimal performance. A list of possible clocking structures is provided in High-Speed IOSERDES2 Usage for Advanced Serialization.

SDR Data Rate (FD Register in IOB, No IOSERDES2)

Two SelectIO options for registering data into the device.

•Figure 1-12 uses a BUFIO2 (IOCLK) to drive the I/O flip-flop with BUFG (BUFIO2DIVCLK) to drive FPGA logic registers. There is a routing delay through the BUFG. Works with or without IODELAY2.

•Figure 1-13 uses a BUFG (GCLK) to drive both FPGA logic and I/O. Works with or without IODELAY2.

Figure 1-12: I/O Flip-Flop Clocking using BUFIO2

FPGA

Logic

UG382_c2_10_121709

Figure 1-13: I/O Flip-Flop Clocking using BUFG