Clock Inputs

DDR Data Rate (IDDR2, ODDR2, No IOSERDES2)

The following options can be used for clocking IDDR2 and ODDR2 primitives.

•When performance is not critical, use a single DCM output to drive both clock (C0) and the inverted clock (C1) using local inversion. Works with or without IODELAY2.

•For the highest performance, use two DCM outputs with separate BUFGs with 180° phase difference. Works with or without IODELAY2. See Figure 1-18.

•If not using a DCM, then the GCLK input should directly drive two BUFIO2s. Use two BUFIO2s with the first BUFIO2 (USE_DOUBLER) for C0 and an inverted clock using BUFIO2 (I_INVERT = TRUE) for C1 connected to the same GCLK. FPGA logic is driven by BUFG (C0 BUFIO2-DIVCLK). There is a routing delay through the BUFG.

•Using an IODELAY2 requires the IBUFGDS_DIFF_OUT. (See Figure 1-35, page 50)

•A single-ended input with IODELAY2 is not supported.

•For bidirectional interfaces, input and output logic must both use the same data rate (IDDR2 and ODDR2). Mixing SDR and DDR bidirectional I/Os are not permitted.

High-Speed IOSERDES2 Usage for Advanced Serialization

IOSERDES2 (SDR)

IOSERDES2 (SDR) requires one BUFIO2. BUFIO2 (USE_DOUBLER = FALSE and I_INVERT = FALSE) with IOCE driven by BUFIO2-SERDESSTROBE and CLKDIV driven by BUFG (BUFIO2-DIVCLK). FPGA logic driven by BUFG (BUFIO2 - DIVCLK). The SERDESSTROBE resolves the BUFG routing delays. Works with or without IODELAY2. See Figure 1-14.

IOSERDES2 (DDR)

IOSERDES2 (DDR) requires two BUFIO2s. Use first BUFIO2 (USE_DOUBLER = TRUE) with IOCE driven by BUFIO2 (SERDESSTROBE) and CLKDIV driven by BUFG (BUFIO2DIVCLK). Second BUFIO2 uses (I_INVERT = TRUE, USE_DOUBLER = FALSE) to drive C1 clock input. The SERDESSTROBE resolves the BUFG routing delays. See Figure 1-15.

•Using an IODELAY2 requires the IBUFGDS_DIFF_OUT. (See Figure 1-31, page 45).

•Single-ended input with IODELAY2 is not supported in this case.

IOSERDES2 with PLL

Only SDR is supported. The GCLK inputs drive the inferred BUFIO2’s DIVCLK output, which drives the PLL clock input. The PLL uses two clock outputs to drive the BUFPLL’s PLLIN input and the BUFPLL’s GCLK input from the BUFG output. Connect the BUFPLL’s LOCKED input to the PLL’s LOCKED output. Works with or without IODELAY2. See Figure 1-16.

For bidirectional interfaces, input and output logic must set DATA_RATE identically for input logic and output logic. Mixing SDR and DDR bidirectional I/Os is not permitted.

Spartan-6 FPGA Clocking Resources www.xilinx.com 31