Chapter 2: Clock Management Technology

VIDEO_LINK_M0, VIDEO_LINK_M1, and VIDEO_LINK_M2 are selected to cover typical pixel clock frequencies. VIDEO_LINK_M0 has the fastest modulation frequency response to help compensate for the higher periods associated with 20 MHz pixel clocks. Actual modulation frequency depends on the SSCLKGEN setup. VIDEO_LINK_M1 is slower and VIDEO_LINK_M2 is the slowest.

Pixel clock frequencies of CLKFX_MULTIPLY = 7, CLKFX_DIVIDE = 2 are used when the maximum CLKOUT_FREQ_FX is maintained. For higher pixel clock frequencies, DCM_CLKGEN must be changed to CLKFX_MULTIPLY = 7 and CLKFX_DIVIDE = 4 to compensate for the PLL addition. See Figure 2-19. This slows down the modulation frequency requiring VIDEO_LINK_M1.

Figure 2-19: VIDEO_LINK Setup for Downspread Spread Spectrum (when FIN > 107 MHz)

Free-Running Oscillator

The DCM_CLKGEN can be used to generate a clock source by tieing the LOCKED output pin to the FREEZEDCM input pin. The DCM requires a kick-start in this mode; instead of an always running clock, any oscillating signal can be used until the DCM has LOCKED. Figure 2-20 illustrates an example.

CLKFX_MULTIPLY = ?

CLKFX_DIVIDE = ?

DCM_CLKGEN

CLKFX

Keeps toggling at a

steady and fixed

rate until LOCK is FREEZEDCM

achieved.

LOCKED

CLKFX_MULTIPLY

FCLKFX = FCLKIN x

CLKFX_DIVIDE

UG382_c2_14_120809

Figure 2-20: Setup of a Free-Running Oscillator

Chapter 2: Clock Management Technology