General Usage Description

Counter Clock Input

(VCO)

DIVIDE = 2

DUTY_CYCLE = 0.5

PHASE = 0

DIVIDE = 2

DUTY_CYCLE = 0.5

PHASE = 180

DIVIDE = 2

DUTY_CYCLE = 0.75

PHASE = 180

DIVIDE = 1

DUTY_CYCLE = 0.5

PHASE = 0

DIVIDE = 1

DUTY_CYCLE = 0.5

PHASE = 360

DIVIDE = 3

DUTY_CYCLE = 0.33

PHASE = 0

DIVIDE = 3

DUTY_CYCLE = 0.5

PHASE = 0

ug382_c3_07_080309

Figure 3-8: Output Counter Clock Synthesis Examples

Clock Shifting

The PLL output clocks can be shifted by inserting delay by selecting one of the eight phases in either the reference or the feedback path. Figure 3-9 shows the effect on a clock signal edge at the output of the PLL without any shifting versus the two cases (delay inserted in the feedback path and delay inserted in the reference path).

Spartan-6 FPGA Clocking Resources www.xilinx.com 107