Clock Resources

I/O Clocking Infrastructure

Figure 1-5 illustrates the I/O clocking infrastructure.

BUFIO2 BUFIO2

ug382_c1_03_120809

Figure 1-5: Spartan-6 FPGA I/O Clock Structure in an I/O Bank

All SelectIO logic resources (input registers, output registers, IDDR2, ODDR2, ISERDES2, and OSERDES2) must be driven by a clock coming from either a BUFIO2 located within the same BUFIO2 clocking region, one of the BUFPLLs on the same edge of the device, or one of the 16 BUFGs.

It is important to understand the organization of the BUFIO2 clocking regions for designs using the BUFIO2 for clocking SelectIO logic. There are four high-speed I/O clocks in every BUFIO2 clocking region driven by four dedicated BUFIO2 buffers. There are a total of eight BUFIO2 clocking regions for a total of 32 BUFIO2s. As shown in Figure 1-6, each side of the device is split into two BUFIO2 clocking regions. UG385, Spartan-6 FPGA Packaging and Pinout Specification lists the BUFIO2 clocking region for each pin.

Figure 1-6: BUFIO2 Clocking Regions

Spartan-6 FPGA Clocking Resources www.xilinx.com 21

Chapter 1: Clock Resources

Spanning a Full Bank with a Single Global Clock Input With Two I/O Clocks

It is possible to span an entire bank with a single global clock input that is connected to two BUFIO2 buffers in different BUFIO2 clocking regions to span an entire edge of the device. Figure 1-7 illustrates the connection in Bank 0. Two BUFIO2 resources are used as an example for GCLK19, BUFIO2_X2Y28 and BUFIO2_X4Y28. In Figure 1-7, the dashed lines denote I_INVERT paths. Spanning the entire bank by using two BUFIO2 primitives can only be done when the clock input is directly connected to the BUFIO2 primitive. As a result, the BUFIO2 will be aligned to the rising edge of the clock input. See BUFIO2 clock buffer for additional information. For some applications, an IODELAY2 could be needed to delay the input clock. Because the IODELAY2 can only connect to a single BUFIO2, routing of the delayed GCLK input will be restricted to one BUFIO2 clocking region.

Alternatively, to drive the entire bank when using the IODELAY2 primitive, use the PLL with the BUFPLL primitive.

The I/O clock network can also be driven by a PLL through the BUFPLL buffers. Each PLL has two associated buffers that each span an entire I/O bank.

Note: Using IODELAY2 clocking with a full bank is not supported.