Clock Buffers and Multiplexers
S
I0
I1
O
ug382_1_16_120809
Figure 1-24: BUFGMUX_1 (CLK_SEL_TYPE = SYNC) Timing Diagram
In Figure 1-24:
•The current clock is I0.
•S is activated High.
•If I0 is currently Low, the multiplexer waits for I0 to be asserted High.
•Once I0 is High, the multiplexer output stays High until I1 transitions Low to High.
•When I1 transitions from Low to High, the output switches to I1.
•No glitches or short pulses can appear on the output.
BUFG
The BUFGMUX is the physical clock buffer in the device, but it can be used as a simple single-input clock buffer. The BUFG clock buffer primitive (see Figure 1-25) drives a single clock signal onto the clock network and is essentially the same as a BUFGMUX, without the clock select mechanism. BUFG is the generic primitive for clock buffers across multiple Virtex and Spartan architectures.
BUFG
O
I
ug382_c1_17_120809
Figure 1-25: BUFG Primitive
The BUFG is built from the BUFGMUX as shown in Figure 1-26.
BUFGMUX
I1
O
I I0
S
GND
ug382_c1_18_120809
Figure 1-26: BUFG Built from a BUFGMUX
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Chapter 1: Clock Resources
BUFGCE and BUFGCE_1
The BUFGCE primitive creates an enabled clock buffer using the BUFGMUX select mechanism (see Figure 1-27). BUFGCE is a global clock buffer with a single gated input. Its O output is 0 when clock enable (CE) is Low (inactive). When clock enable (CE) is High, the I input is transferred to the O output. The BUFGCE truth table is shown in Table 1-15.
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CE |
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Figure 1-27: BUFGCE Primitive |
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Table 1-15: BUFGCE Truth Table |
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S Input |
O Output |
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The BUFGCE is built from the BUFGMUX by multiplexing a fixed value for one input. The default value is Low when disabled. The BUFGCE_1 primitive is similar with VCC connected to I1, making the output High when disabled. It also uses the BUFGMUX_1 primitive to provide glitchless operation during the transition between inputs.
Figure 1-28 shows the equivalent functionality, although the library element truly is a primitive. The CE inversion is built into the BUFGMUX functionality. The 0 source can be fed from any convenient unused LUT.
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BUFGMUX |
GND |
I1 |
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I0
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INV
CE_IN
ug382_c1_20_120809
Figure 1-28: Equivalent Functionality of BUFGCE
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Clock Buffers and Multiplexers
BUFH
The horizontal clock buffer (BUFH) allows access to one half of an HCLK row clock. The BUFH clock primitive (see Figure 1-29) drives a single clock signal in the half of the HCLK row. The BUFH is used to clock interconnect logic, SelectIO logic, DSP48A1 tiles, or block RAM resources. The BUFH is accessed using FPGA interconnect logic or directly using any clock output from a DCM, PLL, or GTPA1_DUAL tile in the same HCLK row.
BUFH
I O
UG382_c1_28_060310
Figure 1-29: BUFH Primitive
Similar to the BUFG restrictions, the BUFH clock buffers are designed to drive clock signals. When a BUFH is used to reset or set interconnect logic, its placement is limited to the top eight BUFH locations in the HCLK row. When used as an asynchronous set or reset for a block RAM, as a clock enable, or as combinatorial logic, the only the lower eight BUFH locations can be used.
BUFH is not recommended for the DCM feedback path or PLL feedback path.
Clock Buffers for the High-Speed I/O Clock Region
To improve the performance of the I/O tile, Spartan-6 FPGAs contain a dedicated I/O clock network for the connections where performance is most critical. I/O clock buffers Table 1-16 work with the IODELAY2, IDDR2, ODDR2, ISERDES2, and OSERDES2 logic in the I/O tile by connecting to both the I/O clock network and the FPGA logic. The I/O clock buffer outputs restricted to the I/O clock network are listed in Table 1-17.
Table 1-16: I/O Clock Buffers
Primitive |
Input |
Output |
Control |
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BUFIO2 |
I |
IOCLK, DIVCLK, SERDESSTROBE |
– |
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BUFIO2_2CLK |
I, IB |
DIVCLK, IOCLK, SERDESSTROBE |
– |
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BUFPLL |
GCLK, PLLIN, LOCKED |
IOCLK, SERDESSTROBE, LOCK |
– |
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BUFPLL_MCB |
PLLIN0, PLLIN1 |
IOCLK0, IOCLK1, SERDESSTROBE0, |
– |
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BUFIO2FB |
I |
O |
– |
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Chapter 1: Clock Resources
Table 1-17 lists ports that can be used on the I/O clock network.
Table 1-17: I/O Clock Network Signals
Primitive |
I/O Clock Network Inputs |
I/O Clock Network Outputs |
Resource |
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BUFIO2 |
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IOCLK(1), SERDESSTROBE(1) |
I/O Clock Buffer |
BUFIO2_2CLK |
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IOCLK(1), SERDESSTROBE(1) |
I/O Clock Buffer |
BUFPLL |
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IOCLK(1), SERDESSTROBE(1) |
I/O Clock Buffer |
BUFPLL_MCB |
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IOCLK0(1), IOCLK1(1), |
I/O Clock Buffer |
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SERDESSTROBE0(1), |
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BUFIO2FB |
I |
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I/O Clock Buffer |
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ILOGIC2 |
C0, C1 |
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I/O Tile Logic |
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OLOGIC2 |
C0, C1 |
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I/O Tile Logic |
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ISERDES2 |
CLK0, CLK1, IOCE |
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I/O Tile Logic |
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OSERDES2 |
CLK0, CLK1, IOCE |
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I/O Tile Logic |
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IODELAY2 |
IOCLK0, IOCLK1 |
DATAOUT |
I/O Tile Logic |
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GTP_DUAL |
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CLKOUT0[1:0], CLKOUT1[1:0] |
GTP_DUAL Tile |
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Notes:
1. Outputs only to the I/O clock network. Does not connect to FPGA logic.
Each IOLOGIC supports up to three clocks coming from the I/O clock network. Each
IOCLK can be connected to one of eight possible clock sources:
•Two BUFGMUX clock connections. At least one of the clocks must come from BUFGMUX_X2Y[4:1] or BUFGMUX_X3Y[8:5]
•Four BUFIO2 routing connections from a BUFIO2 in the same BUFIO2 clocking region
•Two BUFPLL routing connections from a BUFPLL in the same edge of the device.
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