Chapter 3: Phase-Locked Loops

PLL with Internal Feedback

The PLL feedback can be internal to the PLL when the PLL is used as a synthesizer or jitter filter and there is no required phase relationship between the PLL input clock and the PLL output clock. The PLL performance should increase since the feedback clock is not subjected to noise on the core supply since it never passes through a block powered by this supply. Of course, noise introduced on the CLKIN signal and the BUFG will still be present (Figure 3-12).

COMPENSATION = INTERNAL

UG382_c3_12_060310

Figure 3-12: PLL with Internal Feedback

Zero Delay Buffer

The PLL can also be used to generate a zero delay buffer clock. A zero delay buffer can be useful for applications where there is a single clock signal fan out to multiple destinations with a low skew between them. This configuration is shown in Figure 3-13 for singleended clocks. In Spartan-6 FPGAs, the BUFIO2FB and BUFIO2 placements must be matched and the feedback clock must be placed on the differential pair of the GCLK pin being used. In the case of a differential clock input where both pins of the differential clock are already being used, Figure 3-14 shows a circuit description using the equivalent GCLK in the neighboring BUFIO2 clocking region.

Note: There is an additional inversion of the OB output of the IBUFGDS_DIFF_OUT. This circuit will directly connect the differential GCLK to the matched BUFIO2FB.

The feedback signal is driven off the devices and the board-trace feedback is designed to match the trace to the external components. In this configuration, it is assumed that the clock edges are aligned at the input of the FPGA and the input of the external component. In this example, CLK_FEEDBACK = CLKFBOUT and the output logic is matched to a BUFG driving output logic with all signals using a single-ended I/O standard.

In some cases precise alignment is not possible because of the difference in loading between the input capacitance of the external component and the feedback path capacitance of the FPGA. For example, external components with an input capacitance of 1 pF to 4 pF where the FPGA has an input capacitance of around 8 pF. There is a difference in the signal slope, which is basically skew. To ensure timing, designers need to be aware of this effect.

PLL Use Models

Figure 3-13: Zero Delay Buffer for Single-Ended Clocks

Note: When planning pinouts for a design using external feedback, the tools automatically match the BUFIO2FB and BUFIO2 to ensure optimal phase alignment.

For optimal placement, the input pad for the feedback clock must be placed on the differential pair. For example, if GCLK19 is used for CLKIN, then use GCLK18 for the CLKFB_IN. See Table 1-6 for a complete placement list of global clock input pins.

As shown in Figure 3-14, a BUFIO2 from an adjacent BUFIO2 clocking region is used if either the input clock or the feedback clock are differential clocks. For example, since CLKIN_P and CLKIN_N are connected to GCLK19 and GCLK18 respectively, then CLKFB_IN_P is connected to GCLK15 and CFLKB_IN_N is connected to GCLK14.

Spartan-6 FPGA Clocking Resources www.xilinx.com 111