Chapter 2: Clock Management Technology

PSCLK clock period. Between enabling PSEN until PSDONE is asserted, the DCM output clocks slide, bit by bit, from their original phase shift value to their new phase shift value. During this time, the DCM remains locked on the incoming clock and continues to assert its LOCKED output.

PSDONE indicates that the PS unit completed the previous adjustment and is now ready for the next request. The PHASE_SHIFT attribute value sets the initial phase shift location, established after FPGA configuration. If the DCM is reset, the PHASE_SHIFT value reverts to its initial configuration value.

Variable phase shifting is performed using delay elements. As such, there is a physical maximum for the number of steps, depending on the CLKIN input period (TCLKIN), as shown in Table 2-4.

Table 2-4: Maximum Number of DCM Delay Steps for Variable Phase Shift

For example, assume that the CLKIN clock entering the DCM is 100 MHz, which equates to a clock period of TCLKIN = 10 ns. Using the equation in Table 2-4, the Variable Phase Shifter is limited to phase shift operations of ±105 steps. This equates to a maximum variable phase shift measured in time of up to ±1.05 ns to ±4.2 ns. Measured in degrees, this equates to a maximum between ±37.8° and ±151.2°.

Status Logic

The status logic indicates the current state of the DCM via the LOCKED and STATUS output signals. The LOCKED output signal indicates whether the DCM outputs are in phase with the CLKIN input. The STATUS output signals indicate the state of the DLL and PS operations.

The RST input signal resets the DCM logic and returns it to its post-configuration state. Likewise, a reset forces the DCM to reacquire and lock to the CLKIN input.