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DCM_SP Design Guidelines |
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Table 2-9: DCM_CLKGEN Attributes (Cont’d) |
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Attribute |
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Allowed Settings and Description |
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CLKFXDV_DIVIDE |
Defines the division factor for the frequency of the CLKFXDV output. Allowable values |
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are 2, 4, 8, 16, 32. Default value is 2. |
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F |
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FCLKFX |
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CLKFXDV |
= ------------------------------------------------------- |
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CLKFXDV_DIVIDE |
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CLKFX_MD_MAX |
When dynamic programming of M and D values is engaged, this attribute specifies the |
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maximum ratio of the M and D. CLKFX_MD_MAX is mainly used for static timing |
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analysis. Default value is: |
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CLKFX_MULTIPLY |
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-------------------------------------------------------- |
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CLKFX_DIVIDE |
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DFS_BANDWIDTH |
Reserved. |
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PROG_MD_BANDWIDTH |
Reserved. |
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SPREAD_SPECTRUM |
CENTER_LOW_SPREAD, CENTER_HIGH_SPREAD, VIDEO_LINK_M0(1), |
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VIDEO_LINK_M1(1), VIDEO_LINK_M2(1), NONE |
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STARTUP_WAIT |
Controls whether the FPGA configuration signal DONE waits for the DCM to assert its |
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LOCKED signal before transitioning High. In the starting configuration sequence, GTS |
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must be deasserted for the DCM to lock. |
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FALSE: Default. DONE is asserted at the end of configuration without waiting for the |
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DCM to assert LOCKED. |
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TRUE: The DONE signal does not transition High until the LOCKED signal transitions |
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High on the associated DCM. STARTUP_WAIT does not prevent LOCKED from |
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transitioning High. The FPGA startup sequence must also be modified to insert a LCK |
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(lock) cycle before the postponed cycle. The DONE cycle or GWE cycle are typical |
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choices. |
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When more than one DCM is configured, the FPGA waits until all DCMs are LOCKED. |
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CLKIN_PERIOD |
Specifies the CLKIN period in order to optimize the CLKFX/CLKFX180 outputs. This in |
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turn will result in a faster locking time. Any real number is acceptable. Default value is 0. |
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CLKFX_MD_MAX |
When dynamic programming of M and D values is engaged or when |
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SPREAD_SPECTRUM is used, this attribute specifies the maximum ratio of the M and D. |
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CLKFX_MD_MAX is mainly used for static timing analysis. Floating point value. Default |
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value is CLKFX_MULTIPLY/CLKFX_DIVIDE. |
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Notes:
1.Soft modes of spread spectrum requires an external state machine for correct operation. PROGCLK and PROGDATA must be connected to an external state machine to create a spread-spectrum clock source.
DCM_SP Design Guidelines
Input Clock Frequency Range
The DCM clock input frequency depends on whether the DLL, the DFS, or both are utilized in the application.
The Spartan-6 FPGA data sheet specifies the clock input, CLKIN, and the frequency range for both the DFS and the DLL. The DFS, when used stand-alone, has a wider frequency
Spartan-6 FPGA Clocking Resources www.xilinx.com 77
UG382 (v1.10) June 19, 2015 |
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