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Chapter 2: Clock Management Technology

DATA

REG

REG

REG

 

Source Synchronous Clock

 

(Edge Aligned)

DCM Clock

 

 

DCM

DATA

DATA

Source Synchronous Clock (Edge Aligned)

DCM Clock

DESKEW_ADJUST = SOURCE_SYNCHRONOUS

PHASE_SHIFT= 0

DCM Clock

DESKEW_ADJUST = SOURCE_SYNCHRONOUS

PHASE_SHIFT= 126

PHASE_SHIFT = 126

UG382_c2_21_062812

Figure 2-5: Source Synchronous Edge Aligned

Digital Frequency Synthesizer

The Digital Frequency Synthesizer (DFS) provides a wide and flexible range of output frequencies based on the ratio of two user-defined integers, a multiplier (CLKFX_MULTIPLY) and a divisor (CLKFX_DIVIDE). The output frequency is derived from the input clock (CLKIN) by simultaneous frequency division and multiplication. The DFS feature can be used in conjunction with or separately from the DLL feature of the DCM. If the DLL is not used, then there is no phase relationship between CLKIN and the DFS outputs.

The DFS unit generates the frequency synthesizer (CLKFX and CLKFX180) outputs.

Phase Shift

The DCM provides coarseand fine-grained phase shifting. For coarse-grained phase control, the CLK0, CLK90, CLK180, and CLK270 outputs are each phase-shifted by ¼ of the input clock period relative to each other. Similarly, CLK2X180 and CLKFX180 provide a 180° coarse phase shift of CLK2X and CLKFX, respectively.

For fine-grained phase control, the DCM can optionally phase shift all of its clock outputs using the phase shift (PS) controls. The PS controls the phase relations of the DCM clock outputs to the CLKIN input. A phase shift offset, using the PHASE_SHIFT attribute, can be used in either fixed phase-shift (CLKOUT_PHASE_SHIFT=FIXED) or variable phase shift

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Spartan-6 FPGA Clocking Resources

 

UG382 (v1.10) June 19, 2015