- •Revision History
- •Table of Contents
- •About This Guide
- •Guide Contents
- •Additional Documentation
- •Additional Resources
- •Summary
- •Introduction
- •Clock Resources
- •Global Clocking Infrastructure
- •I/O Clocking Infrastructure
- •Spanning a Full Bank with a Single Global Clock Input With Two I/O Clocks
- •Clock Inputs
- •Clocking Structure Guidelines
- •SDR Data Rate (FD Register in IOB, No IOSERDES2)
- •DDR Data Rate (IDDR2, ODDR2, No IOSERDES2)
- •High-Speed IOSERDES2 Usage for Advanced Serialization
- •IOSERDES2 (SDR)
- •IOSERDES2 (DDR)
- •IOSERDES2 with PLL
- •Examples of High-Speed I/O Clock Network Connections
- •Clock Buffers and Multiplexers
- •Global Clock Input Buffer Primitives
- •Global Clock Buffer Primitives
- •BUFGMUX
- •BUFGMUX_1
- •BUFG
- •BUFGCE and BUFGCE_1
- •BUFH
- •Clock Buffers for the High-Speed I/O Clock Region
- •BUFIO2
- •BUFIO2_2CLK
- •BUFPLL
- •BUFPLL_MCB
- •BUFIO2FB
- •Clock Management Summary
- •DCM Summary
- •DCM Introduction
- •Compatibility and Comparison with Other Xilinx FPGA Families
- •DCM Functional Overview
- •Delay-Locked Loop
- •Skew Adjustment
- •Digital Frequency Synthesizer
- •Phase Shift
- •Fixed Phase Shift
- •Variable Phase Shift
- •Example 1
- •Example 2
- •Status Logic
- •DCM Primitives
- •DCM_SP Primitive
- •DCM_CLKGEN Primitive
- •DCM_SP Design Guidelines
- •Input Clock Frequency Range
- •Output Clock Frequency Range
- •Input Clock and Clock Feedback Variation
- •Cycle-to-Cycle Jitter
- •Period Jitter
- •DLL Feedback Delay Variance
- •Spread Spectrum Clock Reception
- •Optimal DCM Clock and External Feedback Inputs
- •LOCKED Output Behavior
- •Using the LOCKED Signal
- •RST Input Behavior
- •DCM_CLKGEN Design Guidelines
- •Dynamic Frequency Synthesis
- •Spread-Spectrum Clock Generation
- •Spread-Spectrum Generation
- •Fixed Spread Spectrum
- •Soft Spread Spectrum
- •Free-Running Oscillator
- •Introduction
- •Phase Lock Loop (PLL)
- •Aligning PLL using CLK_FEEDBACK and BUFIO2FB
- •General Usage Description
- •PLL Primitives
- •PLL_BASE Primitive
- •PLL_ADV Primitive
- •Clock Network Deskew
- •Frequency Synthesis Only
- •Jitter Filter
- •Limitations
- •VCO Operating Range
- •Minimum and Maximum Input Frequency
- •Duty Cycle Programmability
- •Phase Shift
- •PLL Programming
- •Determine the Input Frequency
- •Determine the M and D Values
- •PLL Ports
- •PLL Attributes
- •PLL Clock Input Signals
- •Counter Control
- •Clock Shifting
- •Detailed VCO and Output Counter Waveforms
- •Missing Input Clock or Feedback Clock
- •PLL Use Models
- •Clock Network Deskew
- •PLL with Internal Feedback
- •Zero Delay Buffer
- •Differential BUFIO2FB Zero Delay Buffer Example (Verilog)
- •Differential BUFIO2FB Zero Delay Buffer Example (VHDL)
- •DCM Driving PLL
- •PLL Driving DCM
- •PLL to PLL Connection
- •Dynamic Reconfiguration Port
- •Application Guidelines
- •PLL Application Example
Chapter 2: Clock Management Technology
DATA |
REG |
REG |
|
REG |
|
Source Synchronous Clock |
|
(Edge Aligned) |
DCM Clock |
|
|
|
DCM |
DATA |
DATA |
Source Synchronous Clock (Edge Aligned)
DCM Clock
DESKEW_ADJUST = SOURCE_SYNCHRONOUS
PHASE_SHIFT= 0
DCM Clock
DESKEW_ADJUST = SOURCE_SYNCHRONOUS
PHASE_SHIFT= 126
PHASE_SHIFT = 126
UG382_c2_21_062812
Figure 2-5: Source Synchronous Edge Aligned
Digital Frequency Synthesizer
The Digital Frequency Synthesizer (DFS) provides a wide and flexible range of output frequencies based on the ratio of two user-defined integers, a multiplier (CLKFX_MULTIPLY) and a divisor (CLKFX_DIVIDE). The output frequency is derived from the input clock (CLKIN) by simultaneous frequency division and multiplication. The DFS feature can be used in conjunction with or separately from the DLL feature of the DCM. If the DLL is not used, then there is no phase relationship between CLKIN and the DFS outputs.
The DFS unit generates the frequency synthesizer (CLKFX and CLKFX180) outputs.
Phase Shift
The DCM provides coarseand fine-grained phase shifting. For coarse-grained phase control, the CLK0, CLK90, CLK180, and CLK270 outputs are each phase-shifted by ¼ of the input clock period relative to each other. Similarly, CLK2X180 and CLKFX180 provide a 180° coarse phase shift of CLK2X and CLKFX, respectively.
For fine-grained phase control, the DCM can optionally phase shift all of its clock outputs using the phase shift (PS) controls. The PS controls the phase relations of the DCM clock outputs to the CLKIN input. A phase shift offset, using the PHASE_SHIFT attribute, can be used in either fixed phase-shift (CLKOUT_PHASE_SHIFT=FIXED) or variable phase shift
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Spartan-6 FPGA Clocking Resources |
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UG382 (v1.10) June 19, 2015 |
