Clock Buffers and Multiplexers

Each BUFIO2 is limited to routing to a single clock for every I/O interface tile. Consequently, when using DDR clocks, a second clock is required with 180° phase shift (Figure 1-33). An example of using two BUFIO2 clock buffers to create the 180° phase shift is shown in Figure 1-15, page 32.

For optimal performance when using a PLL or a DCM, use a BUFIO2. Each GCLK is associated with two BUFIO2 (see Table 1-1 for a complete listing).

A detailed discussion on how to use the strobe and clock outputs is available at Examples of High-Speed I/O Clock Network Connections, page 32.

BUFIO2_2CLK

The BUFIO2_2CLK (Figure 1-34) has almost the same functionality as the BUFIO2 (USE_DOUBLER = TRUE) except it takes two single-ended clocks or a differential pair (output from IBUFDS_DIFF_OUT). Table 1-20 lists the BUFIO2_2CLK ports. Table 1-21 lists the attributes.

BUFIO2_2CLK

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Clock Buffers and Multiplexers

BUFPLL

The BUFPLL (Figure 1-37) is intended for high-speed I/O routing to generate clocks and strobe pulses for the ISERDES2 (SDR) and OSERDES2 (SDR) primitives. The BUFPLL_MCB contains two BUFPLLs within the same bank. As a result, the BUFPLL_MCB and BUFPLL cannot be used at the same time.

When using the PLL clock outputs, CLKOUT0 or CLKOUT1 must directly connect to the PLLIN clock input. See Figure 1-16, Example 3: Basic PLL ISERDES2 (SDR).

The BUFPLL can be used with the BUFIO2FB to create the PLL feedback clock. When used with the BUFIO2FB, the IOCLK output must be connected to the BUFIO2FB feedback buffer. Additional information on PLL feedback is discussed in Aligning PLL using CLK_FEEDBACK and BUFIO2FB in Chapter 3.

The BUFPLL also aligns the SERDESSTROBE to the IOCLK. To align the SERDESSTROBE, the GCLK and the LOCKED inputs must be connected. The IOCLK output is a buffered version of the input clock. The LOCK output serves the exact same function as the PLL LOCKED signal except it does not go HIGH until the PLL has locked and the BUFPLL has aligned the SERDESSTROBE signal correctly. For BUFPLLs located in BANK0 (top) and BANK2 (bottom), the BUFPLL LOCKED inputs can connect to any of the PLLs located within the same half of the device. An additional multiplexer allows one additional PLL from the opposite half of the device. This additional multiplexer allows BUFPLLs located in BANK0 to be driven by either one of the PLLs placed in the bottom half of the device. Similarly, BUFPLLs located in BANK2 can be driven by one PLL located within the top half of the device. Table 1-22 lists the BUFPLL ports, Table 1-23 lists the attributes.

BUFPLL

LOCK

GCLK

LOCKED

SERDESSTROBE

ug382_c1_27_120809

Figure 1-37: BUFPLL Primitive

Word synchronization is achieved in the BUFPLL by using three signals from the PLL: the high-speed clock, the low-speed clock, and the LOCKED signal. The BUFPLL uses these signals to set the position of the SERDESSTROBE signal relative to the low-speed clock. Due to the varying placements of the PLL and BUFPLL, the initial SERDESSTROBE can vary up to one bit period. The SERDESSTROBE signal controls when data is moved from the high-speed domain to the low-speed domain in either the ISERDES2 or the OSERDES2. This relationship is established once when the LOCKED signal transitions from Low to High and is maintained by a simple counter from that point onwards. The BUFPLL can therefore drive all the input or output SERDES in a single edge of the device, all of which will have the same word synchronization.

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