DCM Functional Overview
DCM Functional Overview
The DCM consists of four distinct functions that can operate independently or in tandem. Figure 2-2 shows a simplified block diagram of a DCM.
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DCM |
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PSINCDEC |
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Phase |
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PSEN |
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PSDONE |
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Shifter |
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PSCLK |
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CLK0 |
Clock |
CLKIN |
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Distribution |
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DLL |
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atStuInpge |
tStutpuOage |
CLK90 |
Delay |
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tepSyaDels |
CLK180 |
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CLKFB |
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CLK270 |
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CLK2X |
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CLK2X180 |
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CLKDV |
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DFS |
CLKFX |
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CLKFX180 |
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RST |
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Status |
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LOCKED |
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Logic |
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STATUS |
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ug382_c2_02_051209 |
Figure 2-2: DCM Functional Block Diagram
Delay-Locked Loop
The Delay-Locked Loop (DLL) provides an on-chip digital deskew circuit that effectively generates clock output signals with a net zero delay. The deskew circuit compensates for the delay on the clock routing network by monitoring an output clock, from either the CLK0 or the CLK2X outputs. The DLL effectively eliminates delay from the external clock input port to the individual clock loads within the device. The well-buffered global network minimizes the clock skew on the network caused by loading differences.
To accurately deskew the input routing, the BUIO2FB buffer must be used as shown in Figure 1-40, page 56. The BUFIO2FB is matched to the primary BUFIO2 buffer limiting the deskewing to a single DCM.
The input signals to the DLL unit are CLKIN and CLKFB. The output signals from the DLL are CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
The DLL unit generates the outputs for the clock doubler (CLK2X, CLK2X180), the clock divider (CLKDV) and the quadrant phase-shift functions.
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Chapter 2: Clock Management Technology
Skew Adjustment
DCM_SP allows for different skew adjustments to help with different interfaces. The feedback circuitry adjusts for placement and routing differences based on the location of the DCM and clock buffers. See Figure 1-18 for an example of the recommended feedback structure. DESKEW_ADJUST allows for a small, fixed amount of delay adjustment.
System synchronous and source synchronous are descriptions of different types of interfaces. UG612, Timing Closure User Guide contains descriptions of how to constrain these types of interfaces depending on how the clock and data are aligned. Additional source synchronous interfaces are additionally covered in XAPP1064, Source-Synchronous Serialization and Deserialization (up to 1050 Mb/s).
System synchronous interfaces (Figure 2-3) are the more commonly used type of interface. In this interface, a small fixed amount of skew adjustment is used to reduce the hold times for the input registers. The system synchronous interface advances the clock internal to the FPGA to help ensure zero hold times. Setting DESKEW_ADJUST = SYSTEM_SYNCHRONOUS shifts the clock as shown in Figure 2-3 to help ensure zero hold times.
System
Synchronous
Clock
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REG |
DATA |
REG |
DCM Clock |
DCM |
DATA |
System Synchronous Clock
DCM Clock
DESKEW_ADJUST= SYSTEM_SYNCHRONOUS
System Synchronous
Clock Skew Adjustment
UG382_c2_19_062812
Figure 2-3: System Synchronous
When using the DCM, DESKEW_ADJUST[SYSTEM_SYNCHRONOUS] has no effect on cascaded DCMs, DCMs using external feedback, or DCMs where the clock source does not come from a global clock input routed through the BUFIO2.
As data rates increase, interfaces rely on the clock forwarded with the data. This is commonly called a source synchronous interface. The clock can be either center aligned or edge aligned with the data window. For source synchronous interfaces with the clock center aligned as shown in Figure 2-4, DESKEW_ADJUST(SOURCE_SYNCHRONOUS)
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DCM Functional Overview
uses the shortest skew adjustment to balance the setup time with the hold time for the input register.
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Source Synchronous Clock |
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DCM Clock |
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DCM |
DATA |
DATA |
Source Synchronous Clock (Center Aligned)
DCM Clock
DESKEW_ADJUST = SOURCE_SYNCHRONOUS
UG382_c2_20_062812
Figure 2-4: Source Synchronous Center Aligned
Some source synchronous interfaces use an edge-aligned clock source as shown in Figure 2-5. Use DESKEW_ADJUST[SOURCE_SYNCHRONOUS] to again balance the setup time with the hold time. Phase shifting of the DCM’s clock output can then be used to adjust the phase based on the data rate being used. The DCM clock is shown without phase shift (PHASE_SHIFT[0]) and with the corrected phase shift (PHASE_SHIFT[126]) for the given example.
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