Clock Inputs

I/O BANK 0

Figure 1-7: I/O Clock Spanning a Full Bank

Clock Inputs

Clock pins accept external clock signals and connect directly to BUFGMUX or BUFIO2 primitives. Clock pins can also be used as general-purpose I/Os. In addition to routing a clock from its input pin onto the I/O clock network, the BUFIO2 also provides a dedicated clock path to PLLs/DCMs and BUFGs. Figure 1-8 illustrates the dedicated clock routes.

Note: Using IODELAY2 clocking with a full bank is not supported.

Spartan-6 FPGA Clocking Resources www.xilinx.com 23

Chapter 1: Clock Resources

Figure 1-8: Dedicated Clock Inputs Routed by BUFIO2

Each Spartan-6 FPGA has:

•Up to 32 global clock inputs located along four edges of the FPGA.

•Eight dedicated clock inputs in the middle of each edge of the device.

•Eight BUFIO2 clocking regions

The 32 GCLK input pins are used to drive clock buffers. A differential clock input requires two global clock inputs which allows up to 16 differential global clock inputs. The P and N inputs follow the same configuration as the standard inputs on the clock input pins. The clock inputs that are paired together are consecutive pins in clock number, an even clock number and the next greater odd value. For example, GCLK0 and GCLK1 are a differential pair as are GCLK20 and GCLK21.

All clock input pins can be represented in a design by the IBUFG primitive (or the IBUFGDS primitive for differential clocks). In general, an IBUFG is inferred by the synthesis tool on any top-level clock port. When more control is necessary, an IBUFG can be instantiated by connecting the I port directly to the top-level port and the O port to a DCM, BUFG, or interconnect logic. Most synthesis tools infer the BUFG automatically when connecting an IBUFG to the clock resources of the FPGA.

The IBUFG and IBUFGDS primitives in Table 1-5 are different configurations of the clock input buffer. These two primitives work in conjunction with the Spartan-6 FPGA I/O resource by setting the IOSTANDARD attribute to the desired standard. Refer to Spartan-6 FPGA SelectIO Resources User Guide for a complete list of possible I/O standards.

Table 1-5: Clock Buffer Primitives

Table 1-6 lists the global clock pin locations where P is the positive and N is the negative side of the differential pairs.

Chapter 1: Clock Resources

Figure 1-9 illustrates a GCLK pin layout for the four bank Spartan-6 devices which include XC6SLX4, XC6SLX9, XC6SLX16, XC6SLX45, XC6SLX45T; and the XC6SLX75/75T, XC6SLX100/100T, and XC6SLX150/150T in the FG(G)484 and CSG484 packages. Input routing to BUFIO2, DCM, PLL, and BUFG resources are shown in Figure 1-9. The BUFIO2 routing to BUFIO2 clocking regions, DCM, PLL, and BUFG resources are also indicated. For devices with four VCCO banks, there are two BUFIO2 clocking regions on each edge of the device.

Chapter 1: Clock Resources

Figure 1-11 shows the GCLK pin layout for the larger devices with the additional bank 4 and bank 5. The devices include the XC6SLX75, XC6SLX75T, and XC6SLX100 in the FG(G)676 package, and the XC6SLX100T, XC6SLX150, and XC6SLX150T in the FG(G)676 and FG(G)900 packages. GCLK20 through GCLK23 are powered from VCCO bank 3 while the IOCLKs connect to BUFIO2 clocking region LT. Similarly, GCLK8 through GCLK11 are powered from VCCO bank 1 while the IOCLKs connect to BUFIO2 clocking region RT.

Designs using BUFIO2s to clock SelectIO logic require additional pin planning considerations. Six bank devices must consider the VCCO IOSTANDARD banking rules and the clock routing of the BUFIO2 clocking regions. Table 1-7 compares the four bank

devices with the six bank devices. Pin planning for VCCO1 and VCCO3 can potentially require clocks to come from two separate BUFIO2 clocking regions. Alternatively, pin

planning based on the RT or LT BUFIO2 clocking regions have the potential to place pins in two separate VCCO banks.