Chapter 2: Clock Management Technology
Table 2-1 summarizes the availability of CMTs, DCMs, and PLLs in each Spartan-6 device.
Table 2-1: Available CMT, DCM, and PLL Resources
Device |
Number of CMTs |
Number of DCMs |
Number of PLLs |
|
|
|
|
XC6SLX4 |
2 |
4 |
2 |
|
|
|
|
XC6SLX9 |
2 |
4 |
2 |
|
|
|
|
XC6SLX16 |
2 |
4 |
2 |
|
|
|
|
XC6SLX25 |
2 |
4 |
2 |
|
|
|
|
XC6SLX25T |
2 |
4 |
2 |
|
|
|
|
XC6SLX45 |
4 |
8 |
4 |
|
|
|
|
XC6SLX45T |
4 |
8 |
4 |
|
|
|
|
XC6SLX75 |
6 |
12 |
6 |
|
|
|
|
XC6SLX75T |
6 |
12 |
6 |
|
|
|
|
XC6SLX100 |
6 |
12 |
6 |
|
|
|
|
XC6SLX100T |
6 |
12 |
6 |
|
|
|
|
XC6SLX150 |
6 |
12 |
6 |
|
|
|
|
XC6SLX150T |
6 |
12 |
6 |
|
|
|
|
To minimize clock skew, use global clock buffers for the clock outputs from the CMT. When clock buffers are limited, CMT clock outputs can optionally be used without a global clock buffer, but all logic is required to be placed within a clock region. Each of these clock regions is 16 CLBs tall, contains up to four 18 Kb block RAMs, and up to four DSP48A1 slices.
DCM Summary
Digital Clock Managers (DCMs) provide advanced clocking capabilities to Spartan-6 FPGA applications. Primarily, DCMs eliminate clock skew, thereby improving system performance. Similarly, a DCM optionally phase shifts the clock output to delay the incoming clock by a fraction of the clock period. DCMs optionally multiply or divide the incoming clock frequency to synthesize a new clock frequency. The DCMs integrate directly with the global low-skew clock distribution network.
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DCM Introduction
DCM Introduction
DCMs integrate advanced clocking capabilities directly into the global clock distribution network. Consequently, DCMs solve a variety of common clocking issues, especially in high-performance, high-frequency applications:
•Eliminate clock skew, either within the device or to external components, to improve overall system performance and to eliminate clock distribution delays.
•Phase shift a clock signal, either by a fixed fraction of a clock period or by incremental amounts.
•Multiply or divide an incoming clock frequency or synthesize a completely new frequency by a mixture of static or dynamic clock multiplication and division.
•Condition a clock, ensuring a clean output clock with a 50% duty cycle.
•Mirror, forward, or rebuffer a clock signal, often to deskew and convert the incoming clock signal to a different I/O standard. For example, forwarding and converting an incoming LVTTL clock to LVDS.
•Clock input jitter filtering
•Free-running oscillator
•Spread-spectrum clock generation
Table 2-2: DCM Features and Capabilities
Feature |
Description |
DCM Signals |
|
|
|
DCMs per device |
Four to 12 DCMs, depending on device size. See |
All |
|
Table 2-1. |
|
|
|
|
Clock input sources |
GCLK input, BUFG output, cascaded DCM or PLL output |
CLKIN |
|
(within the same CMT). General interconnect is allowed |
|
|
but not recommended for optimal performance. |
|
|
|
|
Frequency synthesizer output |
Multiply CLKIN by the fraction (M/D) where |
CLKFX, CLKFX180 |
|
M = {2..256}, D = {1..256} when using the DCM_CLKGEN |
|
|
primitive |
|
|
|
|
Clock divider output |
Divide CLKIN by 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, |
CLKDV |
|
7.5, 8, 9, 10, 11, 12, 13, 14, 15, or 16 |
|
|
|
|
Clock doubler output |
Multiply CLKIN frequency by 2 |
CLK2X, CLK2X180 |
|
|
|
Clock conditioning, duty-cycle |
Always provided on most outputs. |
All |
correction |
|
|
|
|
|
Quadrant phase-shift outputs |
0° (no phase shift), 90° (¼ period), 180° (½ period), |
CLK0, CLK90, |
|
270° (¾ period) |
CLK180, CLK270 |
|
|
|
Half-period phase-shift outputs |
Output pairs with 0º and 180º phase shift, ideal for DDR |
CLK0, CLK180, |
|
applications |
CLK2X, CLK2X180, |
|
|
CLKFX, CLKFX180 |
|
|
|
Variable phase-shifting |
Allows DCM clock outputs to adjust phase shift during |
PSEN, PSINCDEC, |
|
operation |
PSCLK, PSDONE |
|
|
|
General purpose DCM operation |
Number of DCM clock outputs connected to general- |
STATUS, LOCKED |
indicators |
purpose interconnect |
|
|
|
|
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Chapter 2: Clock Management Technology
Compatibility and Comparison with Other Xilinx FPGA Families
The Spartan-6 FPGA includes a very similar DCM design to the Spartan-3E and Extended Spartan-3A family. There are, however, important DCM design differences between the Spartan-6 family and Virtex-5 FPGAs.
Similar to the Spartan-3E and Extended Spartan-3A families, the Spartan-6 FPGA DCMs automatically determine their operating range and are not limited to either a Low or High operating frequency range. Spartan-6 FPGAs implement variable-phase shift operations differently. Spartan-6 FPGAs now include the DCM_CLKGEN primitive to support more advanced features such as jitter reduction, dynamic programming of frequency multiplication, dynamic programming of frequency division, and generation of spreadspectrum clocks. Table 2-3 compares various DCM functions in Xilinx FPGAs.
Table 2-3: DCM Differences between Xilinx FPGAs
Function |
Virtex-5 FPGAs(1) |
Spartan-3E and Extended |
Spartan-6 FPGAs |
|
Spartan-3A FPGAs |
||||
|
|
|
||
|
|
|
|
|
Design primitive |
DCM_BASE |
DCM_SP |
DCM_SP |
|
|
DCM_ADV |
|
DCM_CLKGEN |
|
|
|
|
|
|
Distinct DLL operating frequency |
Two: Low and High |
One |
One |
|
ranges |
|
|
|
|
|
|
|
|
|
Distinct DFS operating frequency |
Two: Low and High |
One |
One |
|
ranges |
|
|
|
|
|
|
|
|
|
Variable phase-shift increment or |
1/256th of CLKIN |
DCM_DELAY_STEP |
DCM_DELAY_STEP |
|
decrement unit |
period (degrees) |
between 15 to 35 ps (time) |
See the Spartan-6 |
|
|
|
|
FPGA data sheet |
|
|
|
|
|
|
DCM VCCAUX voltage supply |
2.5V |
2.5V or 3.3V |
2.5V or 3.3V |
|
Jitter reduction with expense of phase |
No |
No |
Yes |
|
alignment |
|
|
|
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|
|
|
|
|
Dynamic programming of frequency |
No |
No |
Yes |
|
multiplication and division |
|
|
|
|
|
|
|
|
|
Generation of spread-spectrum clocks |
No |
No |
Yes |
|
|
|
|
|
Notes:
1.When converting legacy designs using the Virtex-5 FPGA primitives DCM_ADV or DCM_BASE, use the Spartan-6 FPGA DCM_SP or DCM_CLKGEN primitives instead.
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