Chapter 2: Clock Management Technology

Spread-Spectrum Generation

Spartan-6 FPGAs can generate a spread-spectrum clock source from a standard fixedfrequency oscillator. To generate a spread-spectrum clock source from a fixed-frequency clock source, the DCM_CLKGEN can either use a fixed spread-spectrum solution, providing the simplest implementation, or a soft spread-spectrum solution which adds more flexibility but requires additional logic to continually reprogram DCM_CLKGEN. See Table 2-15.

Table 2-15: DCM_CLKGEN Spread-Spectrum Modes

Notes:

1. Fixed spread-spectrum CLKFX output frequency must be greater than 50 MHz.

Fixed Spread Spectrum

The simplest way to implement spread spectrum uses a fixed mode (Figure 2-16) of the DCM_CLKGEN primitive.

SPREAD_SPECTRUM = < CENTER_LOW_SPREAD,CENTER_HIGH_SPREAD>

Using this fixed mode, the DCM_CLKGEN automatically creates a spread spectrum clock. The modulation frequency is based on the input frequency. Where:

Modulation Frequency = input frequency/1024.

Figure 2-16: Fixed Spread Spectrum

DCM_CLKGEN Design Guidelines

Soft Spread Spectrum

For applications requiring downspread modulation, the DCM_CLKGEN can use one of three spread-spectrum modes to control the rate that the DCM_CLKGEN switches between different programming values. A small counter-based state machine can control DCM_CLKGEN to provide a triangular, spread-spectrum clock source (see Figure 2-17). Because DCM_CLKGEN requires an external state machine for the soft spread spectrum, failure to connect PROGCLK and PROGDATA to logic will result in a DRC error.

Typical video link applications need 7:1 serialization. When using IOSERDES2, clock generation requires using both a DCM_CLKGEN and PLL. DCM_CLKGEN generates the spread-spectrum clock source typically with M = 7 and D = 2. To access high-speed I/O clock networks, the PLL multiplies the clock for up to the full clock frequency required for SDR clocking using the BUFPLL as shown in Figure 2-18.

Figure 2-18: VIDEO_LINK Setup for Downspread Spread Spectrum 20-107 MHz (when FIN × 3.5 < CLKOUT_FREQ_FX)

Spartan-6 FPGA Clocking Resources www.xilinx.com 87