Clock Buffers and Multiplexers

An example of the I/O clock network routing for the three I/O clocks is described in Figure 1-30.

IOCLK (BUFPLL_X1Y0)

IOCLK (BUFPLL_X1Y1)

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Figure 1-30: Available I/O Clock Network Resources For BUFIO2 Clocking Region

BUFIO2

The BUFIO2 takes a GCLK clock input and generates two clock outputs and a strobe pulse as illustrated in Figure 1-31.

BUFIO2

DIVCLK

SERDESSTROBE

ug382_c1_21_120809

Figure 1-31: BUFIO2 Primitive

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Chapter 1: Clock Resources

Table 1-18 lists the BUFIO2 ports. The IOCLK output is a buffered version of the input clock (I). The period and duty-cycle of the DIVCLK output is dependent on the attribute setting listed in Table 1-19.

Table 1-18: BUFIO2 Port List and Definitions

As listed in Table 1-19, when the DIVIDE_BYPASS is set to TRUE, the DIVCLK output is a buffered version of the input clock and the SERDESSTROBE output is driven to 1. When the DIVIDE_BYPASS is set to FALSE then the DIVCLK and SERDESSTROBE outputs will

Clock Buffers and Multiplexers

be the input clock divided by the setting of the divide attribute except when using USE_DOUBLER.

For applications where the I/O clock network is driven by a DDR clock, the USE_DOUBLER must be set to TRUE. Setting USE_DOUBLER = TRUE provides the required DIVCLK and SERDESSTROBE outputs when connected to IOSERDES2 with DATA_RATE = DDR (Figure 1-32). An additional BUFIO2 is required to create the 180° phase shift (see Figure 1-33).

Single Data Rate Clock

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Figure 1-32: BUFIO2 Single Data Rate Clock

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Chapter 1: Clock Resources

Figure 1-33: BUFIO2 Double Data Rate Clock