Chapter 2: Clock Management Technology

range than the DLL. If the application uses both the DLL and DFS, then the more restrictive DLL requirements apply. Table 2-10 outlines the input clock frequency range specification names used in the Spartan-6 FPGA data sheet.

Table 2-10: Input Clock Frequency Range

Output Clock Frequency Range

The DCM output clocks also have a specified frequency range.

Input Clock and Clock Feedback Variation

The DCM expects a stable, monotonic clock input. However, for maximum flexibility, the DCM tolerates a certain amount of clock jitter on the CLKIN input and a reasonable amount of frequency variation on both the CLKIN input and the CLKFB clock feedback input.

There are two types of jitter tolerance on the CLKIN input.

•Cycle-to-cycle jitter

•Period jitter

Cycle-to-Cycle Jitter

Cycle-to-cycle jitter indicates how much the CLKIN input period is allowed to change from one cycle to the next. Table 2-11 outlines the maximum allowable cycle-to-cycle change specification names used in the Spartan-6 FPGA data sheet.

Table 2-11: Maximum Allowable Cycle-to-Cycle Jitter

Period Jitter

The other applicable type of jitter is called period jitter. Period jitter indicates the maximum variation in the clock period over millions of clock cycles. Cycle-to-cycle jitter shows the change from one clock cycle to the next while period jitter indicates the maximum range of change over time. Table 2-12 outlines maximum allowable period jitter specification names used in the Spartan-6 FPGA data sheet.

Table 2-12: Maximum Allowable Period Jitter