Chapter 1: Clock Resources

Clock Resources

The Spartan-6 FPGA clock resources consist of four types of connections:

•Global clock input pads (GCLK)

•Global clock multiplexers (BUFG, BUFGMUX)

•I/O clock buffers (BUFIO2, BUFIO2_2CLK, BUFPLL)

•Horizontal clock routing buffers (BUFH) There are two types of clock networks:

•Global clock network providing low-skew clock routing to the FPGA logic resources

•I/O regional clock networks providing high-performance low-skew clocking to the SelectIO logic resources

BUFGMUX can multiplex between two global clock sources or be used as a simple BUFG clock buffer. The clock buffer can only directly drive the global clock routing resources, which can only drive clock inputs. However, clock inputs on the FPGA logic flip-flops can also come from general-purpose routing, although their use should be limited due to higher skew.

BUFPLL and BUFIO2 are used to drive clocks routed only on the I/O regional clock network with much higher performance than the global clock network. This limits the driving destination only to the input serial-to-parallel logic resources (ISERDES) or output parallel-to-serial logic resources (OSERDES) on each bank of the FPGA.

BUFIO2 can drive ISERDES2 and OSERDES2 for either SDR or DDR clocking. BUFIO2 can also route clock inputs from either a GCLK or a GTP_DUAL tile to a BUFG, DCM, or PLL clock input. BUFIO2_2CLK can be used to replace one of the BUFIO2s required for DDR clocking of the ISERDES2 and OSERDES2.

Similarly, the BUFPLL drives clocks routed to the I/O clock network for SDR clocking. The BUFPLL uses a direct connection from the PLL (CLKOUT0 or CLKOUT1) to drive the I/O regional clock network.

BUFH increases the total number of low-skew clock resources available by providing direct access to horizontal sections of the global clock routing.

Chapter 1: Clock Resources

The HCLK row is entered through a dedicated multiplexer switching clocks between the vertical spine and the PLL or DCM outputs. Each HCLK row hosts either one PLL or two DCMs. The PLL or DCM clock outputs can optionally drive a BUFH within the same HCLK row.

Since there are up to 32 GCLK input pins and only 16 global clock buffers in Spartan-6 devices, every global clock buffer can be driven by one of two GCLK pins. When driving a global clock buffer (BUFG or BUFGMUX) directly with a global clock pin (IBUFG or IBUFGDS), the global clock pins from banks 0, 1, and 5 share the same eight global clock buffers as shown in Table 1-1. Similarly, banks 2, 3, and 4 share eight global clock buffers (Table 1-2).

To illustrate the routing conflict caused by the sharing of BUFGMUX inputs, consider a design using GCLK19 and GCLK11. As Table 1-1 shows, both of the global clocks are connected to BUFGMUX_X2Y1 causing a routing error to be generated.

For more routing flexibility, the BUFIO2 can additionally be used to route to a second global clock buffer when using a BUFIO2 (Table 1-1). When using a BUFIO2, a nominal delay through the BUFIO2 will be incurred. Using the BUFIO2 can also impact clock routing to the I/O clock network. Additional routing information is shown in Spanning a Full Bank with a Single Global Clock Input With Two I/O Clocks, page 22.

When using a differential global clock, the global clock associated with the master side of the differential pair (P) will determine the global clock resource used.

Chapter 1: Clock Resources

Table 1-2: Shared Global Clocking Resources for Bank 2 and Bank 3 (Cont’d)

For designs using GTP transceivers, each GTP reference clock is associated with a BUFIO2. This can affect the global clock pins located in bank 0 or bank 2. For SDR interfaces, Table 1-3 lists the GCLK inputs. For DDR interfaces, a second BUFIO2 can be required to invert the clock using the inverting BUFIO2 placements as shown in Table 1-4.

For a complete listing GTP_DUAL placement please see the placement diagrams in

UG386, Spartan-6 FPGA GTP Transceivers User Guide.

Chapter 1: Clock Resources

Table 1-4: BUFIO2 Input Conflicts for DDR Data Rates (IDDR2, ODDR2, ISERDES2 (DDR), OSERDES2

(DDR))

Notes:

1. Example using an LX100T/LX150T in an FG(G)900 package.