INTRODUCTION

For the HDL specification, it would be a matter of changing the bus references from 15 to 31 in line 2 and 31 to 63 in line 3. This would probably require about four seconds.

HDL File Change Example

BEFORE (16 X 16 MULTIPLIER):

entity MULT is

port(A,B:in std_logic(15 downto 0); Y:out std_logic(31 downto 0));

end MULT;

architecture BEHAVE of MULT is begin

Y <= A * B; end BEHAVE;

AFTER (32 X 32 MULTIPLIER):

entity MULT is

port(A,B:in std_logic(31 downto 0); Y:out std_logic(63 downto 0));

end MULT;

architecture BEHAVE of MULT is begin

Y <= A * B; end BEHAVE;

HDL is also ideal for design re-use. You can share your “library” of parts with other designers at your company, therefore saving and avoiding duplication of effort.

So, now that we have specified the design in a behavioral description, how do we convert this into gates, which is what all logic devices are made of?

The answer is synthesis. The synthesis tool does the intensive work of figuring out what gates to use based on the high-level description file you provide. (Using schematic capture, you would have to do this manually.)

Because the resulting netlist is vendor and device family-specific, you must use the appropriate vendor library. Most synthesis tools support a large range of gate array, FPGA, and CPLD device vendors.

In addition, you can specify optimization criteria that the synthesis tool will take into account when selecting the gate-level selection, also called mapping.

Some of these options include: optimizing the complete design for the least number of gates, optimizing a certain section of the design for fastest speed,

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