IMPLEMENTING FPGAS
The Constraints File
To get the ultimate performance from the device, you must tell the implementation tools what and where performance is required.
This design is particularly slow and timing constraints are unnecessary.
Constraints can also be physical; pin locking is a physical constraint.
For this design, assume that the specification for clock frequency is 100 MHz and that the pin-out has been pre-determined to that of a Spartan-3 device.
There are already some constraints in the UCF from the previous project implementation. It will be necessary to delete these constraints.
Highlight “top_constraints.ucf” in the Source window. Expand the “+” next to User Constraints and double-click Edit Constraints (Text).
Highlight all of the constraints and delete them. Save the UCF and close it.
Double-click on Assign Package Pins.
Alternatively, you can highlight the top level (“top.vhd”) and expand the User Constraints branch.
FIGURE 6-5: PROCESS WINDOW SHOWING ASSIGN PACKAGE PINS
The PACE tool will be launched.
Assign all I/O pins in the Design Object List as follows.
reset |
p36 |
red_light |
p44 |
green_light |
p52 |
clock |
p55 |
amber_light |
p46 |
|
|
Xilinx • 153
PROGRAMMABLE LOGIC DESIGN -- QUICK START HANDBOOK • CHAPTER 6
Save and Exit the PACE session.
Double-click on Create Timing Constraints in the Process window, as seen above Assign Package Pins in Figure 6-5.
Notice that the Constraints Editor is invoked and picks up the LOC constraints entered in PACE.
These can be edited by double-clicking on them in the read-write window or under the Ports tab in the Main window.
Double-click in the Period window of the global signal clock and enter a period of 10 ns.
FIGURE 6-6: SPECIFY PERIOD CONSTRAINT
Click OK.
Click on the Ports tab in the Constraints Editor. As there were already constraints in the UCF, they have been imported.
Xilinx • 154
IMPLEMENTING FPGAS
Highlight the three outputs “red_light,” “green_light,” and “amber_light” using ctrl select.
FIGURE 6-7: CONSTRAINTS EDITOR – CREATE GROUP
In the Group Name field, type “lights” and then hit Create Group. In the Select Group box, select lights and hit the Clock to Pad button.
Xilinx • 155
PROGRAMMABLE LOGIC DESIGN -- QUICK START HANDBOOK • CHAPTER 6
In the Clock to Pad dialog box, set the time requirement to 15 ns relative to the clock. There is only one clock, but in some designs there may be more.
FIGURE 6-8: CLOCK TO PAD DIALOG BOX
Click OK.
Notice that the Clock to Pad fields have been filled in automatically. Also notice that the UCF generated has appeared in the UCF Constraints tab at the bottom of the screen.
The UCF file should look similar to Figure 6-9.
FIGURE 6-9: COMPLETE CONSTRAINTS FILE
Xilinx • 156
IMPLEMENTING FPGAS
Save and close the Constraints Editor session.
Click on the “+” next to Implement Design in the Process window.
FIGURE 6-10: PROCESS WINDOW SHOWING IMPLEMENT DESIGN
Implement the design by double-clicking on Implement Design. (You could run each stage separately if required.)
When there is a green tick next to Translate, Map, and Place and Route, your design has completed the implementation stage.
FIGURE 6-11: COMPLETED IMPLEMENTATION
A green tick means that the design ran through without any warnings.
Xilinx • 157