- •Navigating This Book
- •Table of Contents
- •Introduction
- •The History of Programmable Logic
- •Complex Programmable Logic Devices (CPLDs)
- •Why Use a CPLD?
- •Field Programmable Gate Arrays (FPGAs)
- •Design Integration
- •The Basic Design Process
- •HDL File Change Example
- •Before (16 x 16 multiplier):
- •After (32 x 32 multiplier):
- •Intellectual Property (IP) Cores
- •Design Verification
- •Xilinx Solutions
- •Introduction
- •Xilinx Devices
- •Platform FPGAs
- •Virtex FPGAs
- •Virtex-II Pro FPGAs
- •Virtex FPGAs
- •Spartan FPGAs
- •Spartan-3 FPGAs
- •Spartan-IIE FPGAs
- •Spartan-IIE Architectural Features
- •Xilinx CPLDs
- •XC9500 ISP CPLD Overview
- •XC9500XL 3.3V Family
- •XC9500XV 2.5V CPLD Family
- •CoolRunner Low-Power CPLDs
- •CoolRunner-II CPLDs
- •CoolRunner Reference Designs
- •Military and Aerospace
- •Automotive and Industrial
- •Design Tools
- •Design Entry
- •Synthesis
- •Implementation and Configuration
- •Board-Level Integration
- •Verification Technologies
- •Advanced Design Techniques
- •Embedded SW Design Tools Center
- •Xilinx IP Cores
- •Web-Based Information Guide
- •End Markets
- •Silicon Products and Solutions
- •Design Resources
- •System Resources
- •Xilinx Online (IRL)
- •Configuration Solutions
- •Processor Central
- •Tools and Partnerships
- •Memory Corner
- •Silicon
- •Design Tools and Boards
- •Technical Literature and Training
- •Connectivity Central
- •High-Speed Design Resources
- •Signal Integrity Tools
- •Partnerships
- •Signal Integrity
- •Services
- •Xilinx Design Services
- •Education Services
- •Live E-Learning Environment
- •Day Segment Courses
- •Computer-Based Training (CBT)
- •University Program
- •Design Consultants
- •Technical Support
- •Module Descriptions
- •WebPACK Design Suite
- •WebPACK Design Entry
- •WebPACK StateCAD
- •WebPACK MXE Simulator
- •WebPACK HDL Bencher Tool
- •WebPACK FPGA Implementation Tools
- •WebPACK CPLD Implementation Tools
- •WebPACK iMPACT Programmer
- •WebPACK ChipViewer
- •XPower
- •WebPACK CD-ROM Installation
- •Getting Started
- •Licenses
- •Projects
- •Summary
- •Introduction
- •Design Entry
- •The Language Template
- •Close the Language Templates
- •Edit the Counter Module
- •Save the Counter Module
- •Functional Simulation
- •State Machine Editor
- •Top-Level VHDL Designs
- •Top-Level Schematic Designs
- •ECS Hints
- •I/O Markers
- •Implementing CPLDs
- •Introduction
- •Synthesis
- •Constraints Editor
- •CPLD Reports
- •Timing Simulation
- •Configuration
- •Implementing FPGAs
- •Introduction
- •Synthesis
- •The Constraints File
- •FPGA Reports
- •Programming
- •Summary
- •Design Reference Bank
- •Introduction
- •Get the Most out of Microcontroller-Based Designs
- •Conventional Stepper Motor Control
- •Using a Microcontroller to Control a Stepper Motor
- •Stepper Motor Control Using a CPLD
- •PC-Based Motor Control
- •Design Partitioning
- •Conclusion
- •Documentation and Example Code
- •Website Reference
- •ACRONYMS
- •GLOSSARY OF TERMS
PROGRAMMABLE LOGIC DESIGN: QUICK START HANDBOOK • CHAPTER 2
COOLRUNNER REFERENCE DESIGNS
CoolRunner reference designs are HDL code-based designs that can help reduce the time of CPLD designs. They are available free of charge.
These reference designs take the form of not-for-pay IP, which can be used as is. Unlike purchased IP, these reference designs do not come with direct support.
They are built around application notes and have been tested in WebPACK software. They are fully functional through the WebPACK simulator and testbench.
You can find CoolRunner reference designs in the Xilinx IP Center (http://www.xilinx.com/ipcenter/) by searching on the keyword “CoolRunner.”
Accessing the Reference Designs
From the Xilinx.com website, select “Products and Services” from the top bar and then select “Silicon Solutions.” Select “CoolRunner-II CPLDs” from the left-hand side bar and then select “CoolRunner Reference Designs.”
This will bring up a page that details all of the reference designs available for selection. Click on the application note that of interest and download the PDF file. Open the application and go to the last page of the document.
FIGURE 2-41: APPLICATION NOTE REFERENCE DESIGN LINK
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XILINX SOLUTIONS
Click on the link and the following page will appear:
FIGURE 2-42: REFERNECE DESIGN DOWNLOAD INSTRUCTIONS
FIGURE 2-43: “REGISTER ME” LINK
Click on the “Register Me” button to gain access to the free HDL code.
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PROGRAMMABLE LOGIC DESIGN: QUICK START HANDBOOK • CHAPTER 2
.
FIGURE 2-44: LOG IN PAGE
The page above will appear. If you are already a Xilinx registered user, please enter your user name and password.
If you are new to the Xilinx web site, you will need to create an account. Once successful, you will see a page saying “You will receive an e-mail with links to the downloadable files.”
You will then be sent an e-mail listing all of the HDL files, with links to each file. You can then download and start to use any of the HDL design examples in conjunction with your WebPACK software.
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