PROGRAMMABLE LOGIC DESIGN -- QUICK START HANDBOOK • CHAPTER 6

A yellow exclamation point may mean that there is a warning in one of the reports.

A common warning, which can be safely ignored in CPLD designs, is that an “fpga_don’t_touch” attribute has been applied to an instance.

If you’ve followed the design procedure outlined in this example, there should be no errors or warnings.

FPGA Reports

Each stage has its own report. Clicking on the “+” next to each stage lists the reports available:

1.The Translate Report shows any errors in the design or the UCF.

2.The Map Report confirms the resources used within the device and describes trimmed and merged logic. It will also describe exactly where each portion of the design is located in the actual device.

A detailed Map Report can be chosen in the Properties for map.

3.The Post-Map Static Timing Report shows the logic delays only (no routing) covered by the timing constraints. This design has two timing constraints, the clock period and the clock-to-out time of the three lights.

If the logic-only delays don’t meet timing constraints, the additional delay added by routing will only add to the problem.

Without a routing delay, these traffic lights would run at 216 MHz!

4.The Place and Route Report gives a step-by-step progress report.

The place and route tool must be aware of timing requirements. It will list the given constraints and report how comfortably the design fell within – or how much it failed – the constraints.

5.The Asynchronous Delay Report is concerned with the worst path delays in the design – both logic and routing.

6.The Pad Report displays the final pin-out of the design, with information regarding the drive strength and signalling standard.

7.The Guide Report shows how well a guide file has been met (if one was specified).

The Post Place and Route Static Timing Report adds the routing delays. Notice that the max frequency of the clock has dropped.

WebPACK ISE software has additional tools for complex timing analysis and floor planning, which are beyond the scope of this introductory book.

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IMPLEMENTING FPGAS

Programming

Right-click on Generate Programming file and click on Properties.

Under the Start-Up Options tab, ensure that the startup clock is set to JTAG Clock by selecting JTAG Clock from the drop-down menu.

Double-click on Generate Programming File.

This operation creates a .bit file that can be used by the iMPACT programmer to configure a device.

Expand the Generate Programming File tools subsection.

Double-click on Configure Device (iMPACT).

A DLC7 Parallel-IV JTAG cable is required to configure the device from the iMPACT Programmer.

Ensure that the cable is plugged in to the computer and that the ribbon cable/flying leads are connected properly to the board.

You must also connect the power jack of the Parallel-IV cable to either the mouse or keyboard port of the PC.

If the chain specified in the design is not automatically picked up from the ISE tool, right-click in the top half of the iMPACT window and select Add Xilinx Device.

Browse to the location of the project (c:\designs\traffic) and change the file type to .bit.

Open “top.bit” (“top_sch.bit” for schematic designs). The iMPACT Programmer has drawn a picture of the programming chain.

Click on the picture of the device.

From the Operations Menu, select Program.

Summary

This chapter has taken the VHDL or Schematic design through to a working physical device. The steps discussed were:

•Synthesis and Synthesis report

•Timing and Physical Constraints using the Constraints Editor

•The Reports Generated throughout the Implementation flow

•Timing Simulation

•Creating and Downloading a bitstream.

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