- •Navigating This Book
- •Table of Contents
- •Introduction
- •The History of Programmable Logic
- •Complex Programmable Logic Devices (CPLDs)
- •Why Use a CPLD?
- •Field Programmable Gate Arrays (FPGAs)
- •Design Integration
- •The Basic Design Process
- •HDL File Change Example
- •Before (16 x 16 multiplier):
- •After (32 x 32 multiplier):
- •Intellectual Property (IP) Cores
- •Design Verification
- •Xilinx Solutions
- •Introduction
- •Xilinx Devices
- •Platform FPGAs
- •Virtex FPGAs
- •Virtex-II Pro FPGAs
- •Virtex FPGAs
- •Spartan FPGAs
- •Spartan-3 FPGAs
- •Spartan-IIE FPGAs
- •Spartan-IIE Architectural Features
- •Xilinx CPLDs
- •XC9500 ISP CPLD Overview
- •XC9500XL 3.3V Family
- •XC9500XV 2.5V CPLD Family
- •CoolRunner Low-Power CPLDs
- •CoolRunner-II CPLDs
- •CoolRunner Reference Designs
- •Military and Aerospace
- •Automotive and Industrial
- •Design Tools
- •Design Entry
- •Synthesis
- •Implementation and Configuration
- •Board-Level Integration
- •Verification Technologies
- •Advanced Design Techniques
- •Embedded SW Design Tools Center
- •Xilinx IP Cores
- •Web-Based Information Guide
- •End Markets
- •Silicon Products and Solutions
- •Design Resources
- •System Resources
- •Xilinx Online (IRL)
- •Configuration Solutions
- •Processor Central
- •Tools and Partnerships
- •Memory Corner
- •Silicon
- •Design Tools and Boards
- •Technical Literature and Training
- •Connectivity Central
- •High-Speed Design Resources
- •Signal Integrity Tools
- •Partnerships
- •Signal Integrity
- •Services
- •Xilinx Design Services
- •Education Services
- •Live E-Learning Environment
- •Day Segment Courses
- •Computer-Based Training (CBT)
- •University Program
- •Design Consultants
- •Technical Support
- •Module Descriptions
- •WebPACK Design Suite
- •WebPACK Design Entry
- •WebPACK StateCAD
- •WebPACK MXE Simulator
- •WebPACK HDL Bencher Tool
- •WebPACK FPGA Implementation Tools
- •WebPACK CPLD Implementation Tools
- •WebPACK iMPACT Programmer
- •WebPACK ChipViewer
- •XPower
- •WebPACK CD-ROM Installation
- •Getting Started
- •Licenses
- •Projects
- •Summary
- •Introduction
- •Design Entry
- •The Language Template
- •Close the Language Templates
- •Edit the Counter Module
- •Save the Counter Module
- •Functional Simulation
- •State Machine Editor
- •Top-Level VHDL Designs
- •Top-Level Schematic Designs
- •ECS Hints
- •I/O Markers
- •Implementing CPLDs
- •Introduction
- •Synthesis
- •Constraints Editor
- •CPLD Reports
- •Timing Simulation
- •Configuration
- •Implementing FPGAs
- •Introduction
- •Synthesis
- •The Constraints File
- •FPGA Reports
- •Programming
- •Summary
- •Design Reference Bank
- •Introduction
- •Get the Most out of Microcontroller-Based Designs
- •Conventional Stepper Motor Control
- •Using a Microcontroller to Control a Stepper Motor
- •Stepper Motor Control Using a CPLD
- •PC-Based Motor Control
- •Design Partitioning
- •Conclusion
- •Documentation and Example Code
- •Website Reference
- •ACRONYMS
- •GLOSSARY OF TERMS
ACRONYMS
ABEL |
Advanced Boolean Expression Language |
ADC |
Analog-to-Digital Converter |
AIM |
Advanced Interconnect Matrix |
ANSI |
American National Standards Institute |
ASIC |
Application Specific Integrated Circuit |
ASSP |
Application Specific Standard Product |
ATE |
Automatic Test Equipment |
BGA |
Ball Grid Array |
BLVDS |
Backplane Low Voltage Differential Signaling |
BUFG |
Global Clock Buffer |
CAD |
Computer Aided Design |
CAN |
Controller Area Network |
CBT |
Computer Based Training |
CDMA |
Code Division Multiple Access |
CE |
Clock Enable |
CLB |
Configurable Logic Block |
CLK |
Clock Signal |
CMOS |
Complementary Metal Oxide Semiconductor |
CPLD |
Complex Programmable Logic Device |
CPLD |
Complex Programmable Logic Device |
CSP |
Chip Scale Packaging |
DCI |
Digitally Controlled Impedance |
DCM |
Digital Clock Manager |
DCM |
Digital Control Management |
DES |
Data Encryption Standard |
DRAM |
Dynamic Random Access Memory |
DRC |
Design Rule Checker |
DSL |
Digital Subscriber Line |
DSP |
Digital Signal Processor |
DTV |
Digital Television |
ECS |
Schematic Editor |
EDA |
Electronic Design Automation |
EDIF |
Electronic Digital Interchange Format |
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EMI |
Electromagnetic Interference |
EPROM |
Erasable Programmable Read Only Memory |
eSP |
emerging Standards and Protocols |
FAT |
File Allocation Table |
FIFO |
First In First Out |
FIR |
Finite Impulse Response (Filter) |
FIT |
Failures in Time |
FLBGA |
Flip Chip Ball Grid Array |
fMax |
Frequency Maximum |
FPGA |
Field Programmable Gate Array |
FSM |
Finite State Machine |
GPS |
Global Positioning System |
GTL |
Gunning Transceiver Logic |
GTLP |
Gunning Transceiver Logic Plus |
GUI |
Graphical User Interface |
HDL |
Hardware Description Language |
HDTV |
High Definition Television |
HEX |
Hexadecimal |
HSTL |
High Speed Transceiver Logic |
I/O |
Inputs and Outputs |
IBIS |
I/O Buffer Information Specification |
IEEE |
Institute of Electrical and Electronics Engineers |
ILA |
Integrated Logic Analyzer |
IOB |
Input Output Block |
IP |
Intellectual Property |
IRL |
Internet Reconfigurable Logic |
ISE |
Integrated Software Environment |
ISP |
In System Programming |
JEDEC |
Joint Electron Device Engineering Council |
JTAG |
Joint Test Advisory Group |
LAN |
Local Area Network |
LEC |
Logic Equivalence Checker |
LMG |
Logic Modeling Group |
LSB |
Least Significant Bit |
LUT |
Look Up Table |
LVCMOS Low Voltage Complementary Metal Oxide Semiconductor
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ACRONYMS
LVDS |
Low Voltage Differential Signaling |
LVDSEXT Low Voltage Differential Signaling Extension |
|
LVPECL |
Low Voltage Positive Emitter Coupled Logic |
LVTTL |
Low Voltage Transistor to Transistor Logic |
MAC |
Multiply and Accumulate |
MAN |
Metropolitan Area Network |
MCS |
Manipulate Comment Section |
MIL |
Military |
MOSFET |
Metal Oxide Semiconductor Field Effect Transistors |
MP3 |
MPEG Layer III Audio Coding |
MPEG |
Motion Picture Experts Group |
MSB |
Most Significant Bit |
MUX |
Multiplexer |
NAND |
Not And |
NGC |
Native Generic Compiler |
NRE |
Non-Recurring Engineering (Cost) |
OE |
Output Enable |
OTP |
One Time Programmable |
PACE |
Pinout and Area Constraints Editor |
PAL |
Programmable Array Logic |
PCB |
Printed Circuit Board |
PCI |
Peripheral Component Interconnect |
PCMCIA |
Personal Computer Memory Card International Association |
PCS |
Personnel Communications System |
PLA |
Programmable Logic Array |
PLD |
Programmable Logic Device |
PROM |
Programmable Read Only Memory |
QFP |
Quad Flat Pack |
QML |
Qualified Manufacturers Listing |
QPRO |
QML Performance Reliability of Supply Off the Shelf ASIC |
RAM |
Random Access Memory |
RC |
Radio Controlled |
ROM |
Read Only Memory |
SOP |
Sum of Product |
SPLD |
Simple Programmable Logic Device |
SRAM |
Static Random Access Memory |
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SRL16 |
Shift Register LUT |
SSTL |
Stub Series Terminated Transceiver Logic |
TIM |
Time in Market |
Tpd |
Time of Propagation Delay (through the device) |
TQFP |
Thin Quad Flat Pack |
TTM |
Time to Market |
UCF |
User Constraints File |
UMTS |
Universal Mobile Telecommunications System |
UV |
Ultraviolet |
VCCO |
Voltage Current Controlled Oscillator |
VFM |
Variable Function Multiplexer |
VHDL |
VHISC High Level Description Language |
VHSIC |
Very High Speed Integrated Circuit |
VREF |
Voltage Reference |
VSS |
Visual Software Solutions |
WAN |
Wireless Area Network |
WLAN |
Wireless Local Access Network |
WPU |
Weak Pull Up |
XCITE |
Xilinx Controlled Impedance Technology |
XOR |
Exclusive OR |
XST |
Xilinx Synthesis Technology |
ZIA |
Zero Power Interconnect Array |
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