PROGRAMMABLE LOGIC DESIGN -- QUICK START HANDBOOK • CHAPTER 4

Design Entry

To start WebPACK ISE software, select Start > Programs > Xilinx ISE 6 > Project Navigator.

To create a new project, select File > New Project.

FIGURE 4-1: NEW PROJECT WINDOW – PROJECT NAME

Call the project “Traffic” and put it in your Designs directory. For this tutorial, we will be using an HDL top level.

Click the Next> button.

Enter the following into the New Project dialog box:

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WEBPACK ISE DESIGN ENTRY

FIGURE 4-2: NEW PROJECT WINDOW – DEVICE AND DESIGN FLOW

Click the Next> button.

Add a new source to the project by clicking on the New Source button. Add a VHDL module and call it “Counter.”

FIGURE 4-3: NEW SOURCE WINDOW

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PROGRAMMABLE LOGIC DESIGN -- QUICK START HANDBOOK • CHAPTER 4

Click the Next> button.

Create a 4-Bit Counter Module

FIGURE 4-4: DEFINE VHDL SOURCE WINDOW

Declare three ports: “clock,” “reset,” and “count.” The clock and reset ports should both be of direction “in.”

Count should be direction “inout” and should be a 4-bit vector with MSB 3, LSB 0.

Click the Next> button.

Review the contents of the final window and click the Finish button.

This has automatically generated the entity in the counter VHDL module.

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WEBPACK ISE DESIGN ENTRY

Notice that a file called “counter.vhd” has been added to the project in the Sources in Project window of the Project Navigator.

FIGURE 4-5: SOURCE IN PROJECT WINDOW

Double-click on this source to open it in the WebPACK ISE Editor window.

FIGURE 4-6: COUNTER WINDOW

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