WEBPACK ISE DESIGN SOFTWARE
4. Generate Programming File – Creates a programming bitstream. For CPLDs, the implementation process includes:
1.Translate – Interprets the design and runs a “design rule check.”
2.Fit – Allocates resource usage and connections.
3.Generate Programming File – Creates a JED file for programming.
WebPACK Design Suite
TABLE 3-1: WEBPACK DEVICE SUPPORT
Device |
Support |
|
|
Virtex-II Pro |
Up to XC2VP2 |
|
|
Virtex-II |
Up to XC2V250 |
|
|
Virtex-E |
Up to XCV300E |
|
|
Spartan-IIE |
Up to XC2S300E |
|
|
Spartan-II |
Up to XC2S200 |
|
|
Spartan-3 |
Up to XC3S400 |
|
|
CoolRunner-II |
All |
|
|
CoolRunner |
All |
|
|
XC9500 Families |
All |
|
|
WEBPACK DESIGN ENTRY
The WebPACK tool suite supports several different design entries. The XST synthesis tool synthesizes HDL code in VHDL, Verilog, or ABEL into a netlist.
Schematic designs are converted into VHDL or Verilog, which are then synthesized by XST in the same way.
WEBPACK STATECAD
StateCAD is a tool for graphically entering state machines in “bubble diagram” form.
You simply draw the states, transitions, and outputs, and StateCAD gives a visual test facility. State machines are generated in HDL and then added to the WebPACK ISE project.
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PROGRAMMABLE LOGIC DESIGN -- QUICK START HANDBOOK • CHAPTER 3
WEBPACK MXE SIMULATOR
The WebPACK MXE Simulator can be used for both functional and timing simulation. The necessary libraries are already pre-compiled into MXE. Prewritten scripts seamlessly compile the design to be tested, as well as its testbench.
For functional simulation, the written code is simulated before synthesis. After fitting (CPLDs) or place and route (FPGAs), you can simulate the design using the same original testbench as a test fixture, but with logic and routing delays added.
WEBPACK HDL BENCHER TOOL
The HDL Bencher tool generates the testbenches, allowing you to simulate the design under test.
The HDL Bencher tool reads the design under test. You simply enter signal transitions in a graphical timing diagram GUI.
You can also enter your expected simulation results, allowing the simulator to flag a warning if the simulation did not yield the expected results.
WEBPACK FPGA IMPLEMENTATION TOOLS
As we discussed, there are several steps to implementing an FPGA design. Xilinx FPGA implementation tools perform all of these steps.
WEBPACK CPLD IMPLEMENTATION TOOLS
Similarly, CPLD implementation tools perform all of the steps in the CPLD implementation flow outlined previously.
WEBPACK IMPACT PROGRAMMER
The iMPACT programmer module allows you to program a device in-sys- tem for all devices available in the WebPACK software. (You must connect a JTAG cable to the PC’s parallel port.)
For FPGAs, the programmer module allows you to configure a device via the JTAG cable.
Xilinx FPGAs are based on a volatile SRAM technology, so the device will not retain configuration data when you remove the power. Therefore, this configuration method is normally only used for test purposes.
CPLDs, however, are non-volatile devices. Once programmed, they will retain their program until it’s erased or reprogrammed.
The programmer module also includes a PROM file formatter. The use of an external PROM is a popular method of storing FPGA configuration data.
The PROM file formatter takes in the bitstream generated during the implementation phase and provides an MCSor HEX-formatted file used by PROM programmers.
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