- •Table of Contents
- •REVISION HISTORY
- •GNZ, GLS, and GNY BGA packages (bottom view)
- •description
- •device characteristics
- •functional and CPU (DSP core) block diagram
- •CPU (DSP core) description
- •memory map summary
- •peripheral register descriptions
- •DMA synchronization events
- •interrupt sources and interrupt selector
- •signal groups description
- •Signal Descriptions
- •development support
- •Software Development Tools:
- •Hardware Development Tools:
- •device and development-support tool nomenclature
- •TMDX
- •TMDS
- •documentation support
- •clock PLL
- •power-supply sequencing
- •system-level design considerations
- •power-supply design considerations
- •IEEE 1149.1 JTAG compatibility statement
- •recommended operating conditions
- •PARAMETER MEASUREMENT INFORMATION
- •signal transition levels
- •timing parameters and board routing analysis
- •INPUT AND OUTPUT CLOCKS
- •ASYNCHRONOUS MEMORY TIMING
- •SYNCHRONOUS-BURST MEMORY TIMING
- •SYNCHRONOUS DRAM TIMING
- •RESET TIMING
- •EXTERNAL INTERRUPT TIMING
- •EXPANSION BUS SYNCHRONOUS FIFO TIMING
- •EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING
- •EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING
- •EXPANSION BUS ASYNCHRONOUS HOST-PORT TIMING
- •XHOLD/XHOLDA TIMING
- •MULTICHANNEL BUFFERED SERIAL PORT TIMING
- •timing requirements for FSR when GSYNC = 1 (see Figure 48)
- •DMAC, TIMER, POWER-DOWN TIMING
- •JTAG TEST-PORT TIMING
- •timing requirements for JTAG test port (see Figure 56)
- •MECHANICAL DATA
- •thermal resistance characteristics (S-PBGA package)
- •thermal resistance characteristics (S-PBGA package)
- •thermal resistance characteristics (S-PBGA package)
- •IMPORTANT NOTICE
TMS320C6203B
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS086K – JANUARY 1999 – REVISED APRIL 2003
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Signal Descriptions (Continued) |
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SIGNAL |
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PIN NO. |
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TYPE† |
DESCRIPTION |
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GLS/ |
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NAME |
GNZ |
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GNY |
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GROUND PINS (CONTINUED) |
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– |
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AB1 |
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– |
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AB3 |
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– |
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AB7 |
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VSS |
– |
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AB11 |
GND |
Ground pins |
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– |
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AB16 |
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– |
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AB20 |
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– |
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AB22 |
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† I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
development support
TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.
The following products support development of C6000 DSP-based applications:
Software Development Tools:
Code Composer Studio Integrated Development Environment (IDE) including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS ), which provides the basic run-time target software needed to support any DSP application.
Hardware Development Tools:
Extended Development System (XDS ) Emulator (supports C6000 DSP multiprocessor system debug) EVM (Evaluation Module)
For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
Code Composer Studio, DSP/BIOS, XDS, and TMS320 are trademarks of Texas Instruments.
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 |