TMS320C6203B

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS086K – JANUARY 1999 – REVISED APRIL 2003

PARAMETER MEASUREMENT INFORMATION

Figure 8. Test Load Circuit for AC Timing Measurements

signal transition levels

All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.

Vref = 1.5 V

Figure 9. Input and Output Voltage Reference Levels for ac Timing Measurements

All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, and VOL MAX and VOH MIN for output clocks.

Vref = VIH MIN (or VOH MIN)

Vref = VIL MAX (or VOL MAX)

Figure 10. Rise and Fall Transition Time Voltage Reference Levels

TMS320C6203B

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS086K – JANUARY 1999 – REVISED APRIL 2003

PARAMETER MEASUREMENT INFORMATION (CONTINUED)

timing parameters and board routing analysis

The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing differences.

For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin, but also tends to improve the input hold time margins (see Table 19 and Figure 11).

Figure 11 represents a general transfer between the DSP and an external device. The figure also represents board route delays and how they are perceived by the DSP and the external device.

Table 19. Board-Level Timings Examples (see Figure 11)

8

Data Signals‡ (Output from External Device)

† Control signals include data for Writes.

‡ Data signals are generated during Reads from an external device.

Figure 11. Board-Level Input/Output Timings