Аналіз обчислювальної похибки при виконанні базових операцій алгоритмів цифрової обробки сигналів. Обчислення математичних функцій роектування комп’ютерних засобів обробки сигналів та зображень Ваврук. Лаби для 13 групи / MAZ / MAZ-DOD-MAT-2012 / tms320c40

PRODUCTION DATA information is current as of publication date.

Copyright 1996, Texas Instruments Incorporated

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

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2

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

page

PDATA Bus

LA30 ± LA0

LD31 ± LD0

previous

PADDR Bus

LDE

DDATA Bus

LAE

LSTAT3 ± LSTAT0

M

LLOCK

from

DADDR 1 Bus

U

X

LSTRB0 ± LSTRB1

Continued

DADDR 2 Bus

LR / W0 ± LR / W1

LPAGE0 ± LPAGE1

DMADATA Bus

LRDY0 ± LRDY1

LCE0,LCE1

DMAADDR Bus

32

32

MUX

COM Port 0

Input

CREQ0

FIFO

CACK0

DMA Coprocessor

FIFO

PAU

CSTRB0

Ports

Output

CRDY0

DMA Channel 0

BusDataPeripheral

BusAddressPeripheral

Timer 0

C0D7±C0D0

CommunicationSix

DMA Channel 1

Port-Control Registers

DMA Channel 2

DMA Channel 3

DMA Channel 4

COM Port 5

DMA Channel 5

CREQ5

Input

CACK5

FIFO

Six DMA Channels

Output

PAU

CSTRB5

CRDY5

FIFO

C5D7± C5D0

Port-Control Registers

Global-Control Register

TCLK0

Time-Period Register

Timer-Counter Register

Timer 1

Global-Control Register

TCLK1

Time-Period Register

Timer-Counter Register

Port Control

Global

Local

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3

NAME

NO. OF

TYPE²

DESCRIPTION

PINS

GLOBAL-BUS EXTERNAL INTERFACE ( 80 PINS)

D31 ± D0

32

I / O / Z

32-bit data port of the global-bus external interface

1

I

Data-bus-enable signal for the global-bus external interface

DE

A30± A0

31

O / Z

31-bit address port of the global-bus external interface

1

I

Address-bus-enable signal for the global-bus external interface

AE

STAT3 ± STAT0

4

O

Status signals for the global-bus external interface

1

O

Lock signal for the global-bus external interface

LOCK

³

1

O / Z

Access strobe 0 for the global-bus external interface

STRB0

R /

1

O / Z

Read/ write signal for

accesses

W0³

STRB0

PAGE0³

1

O / Z

Page signal for

STRB0

accesses

³

1

I

Ready signal for

accesses

RDY0

STRB0

³

1

I

Control enable for the

PAGE0, and R /

CE0

STRB0,

W0 signals

³

1

O / Z

Access strobe 1 for the global-bus external interface

STRB1

R /

1

O / Z

Read/ write signal for

accesses

W1³

STRB1

PAGE1³

1

O / Z

Page signal for

STRB1

accesses

³

1

I

Ready signal for

accesses

RDY1

STRB1

³

1

I

Control enable for the

PAGE1, and R /

CE1

STRB1,

W1 signals

LOCAL-BUS EXTERNAL INTERFACE ( 80 PINS)

LD31± LD0

32

I / O / Z

32-bit data port of the local-bus external interface

1

I

Data-bus-enable signal for the local-bus external interface

LDE

LA30± LA0

31

O / Z

31-bit address port of the local-bus external interface

1

I

Address-bus-enable signal for the local-bus external interface

LAE

LSTAT3 ± LSTAT0

4

O

Status signals for the local-bus external interface

1

O

Lock signal for the local-bus external interface

LLOCK

³

1

O / Z

Access strobe 0 for the local-bus external interface

LSTRB0

LR /

1

O / Z

Read/ write signal for

accesses

W0

LSTRB0

LPAGE0

1

O / Z

Page signal for

LSTRB0

accesses

1

I

Ready signal for

accesses

LRDY0

LSTRB0

1

I

Control enable for the

LPAGE0, and LR /

LCE0

LSTRB0,

W0 signals

³

1

O / Z

Access strobe 1 for the local-bus external interface

LSTRB1

LR /

1

O / Z

Read/ write signal for

accesses

W1

LSTRB1

LPAGE1

1

O / Z

Page signal for

accesses

LSTRB1

1

I

Ready signal for

accesses

LRDY1

LSTRB1

1

I

Control enable for the

LPAGE1, and LR /

LCE1

LSTRB1,

W1 signals

4

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

TMS320C40

DIGITAL SIGNAL PROCESSOR

SPRS038 ± JANUARY 1996

Pin Functions (Continued)

NAME

NO. OF

TYPE²

DESCRIPTION

PINS

COMMUNICATION PORT 0 INTERFACE ( 12 PINS)

C0D7 ± C0D0

8

I / O

Communication port 0 data bus

1

I / O

Communication port 0 token-request signal

CREQ0

1

I / O

Communication port 0 token-request-acknowledge signal

CACK0

1

I / O

Communication port 0 data-strobe signal

CSTRB0

1

I / O

Communication port 0 data-ready signal

CRDY0

COMMUNICATION PORT 1 INTERFACE ( 12 PINS)

C1D7 ± C1D0

8

I / O

Communication port 1 data bus

1

I / O

Communication port 1 token-request signal

CREQ1

1

I / O

Communication port 1 token-request-acknowledge signal

CACK1

1

I / O

Communication port 1 data-strobe signal

CSTRB1

1

I / O

Communication port 1 data-ready signal

CRDY1

COMMUNICATION PORT 2 INTERFACE ( 12 PINS)

C2D7 ± C2D0

8

I / O

Communication port 2 data bus

1

I / O

Communication port 2 token-request signal

CREQ2

1

I / O

Communication port 2 token-request-acknowledge signal

CACK2

1

I / O

Communication port 2 data-strobe signal

CSTRB2

1

I / O

Communication port 2 data-ready signal

CRDY2

COMMUNICATION PORT 3 INTERFACE ( 12 PINS)

C3D7 ± C3D0

8

I / O

Communication port 3 data bus

1

I / O

Communication port 3 token-request signal

CREQ3

1

I / O

Communication port 3 token-request-acknowledge signal

CACK3

1

I / O

Communication port 3 data-strobe signal

CSTRB3

1

I / O

Communication port 3 data-ready signal

CRDY3

COMMUNICATION PORT 4 INTERFACE ( 12 PINS)

C4D7 ± C4D0

8

I / O

Communication port 4 data bus

1

I / O

Communication port 4 token-request signal

CREQ4

1

I / O

Communication port 4 token-request-acknowledge signal

CACK4

1

I / O

Communication port 4 data-strobe signal

CSTRB4

1

I / O

Communication port 4 data-ready signal

CRDY4

COMMUNICATION PORT 5 INTERFACE ( 12 PINS)

C5D7 ± C5D0

8

I / O

Communication port 5 data bus

1

I / O

Communication port 5 token-request signal

CREQ5

1

I / O

Communication port 5 token-request-acknowledge signal

CACK5

1

I / O

Communication port 5 data-strobe signal

CSTRB5

1

I / O

Communication port 5 data-ready signal

CRDY5

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

5

Pin Functions (Continued)

NAME

NO. OF

TYPE²

DESCRIPTION

PINS

INTERRUPTS, I / O FLAGS, RESET, TIMER ( 12 PINS)

IIOF3±

IIOF0

4

I / O

Interrupt and I / O flags

1

I

Nonmaskable interrupt.

is sensitive to a low-going edge.

NMI

NMI

1

O

Interrupt acknowledge

IACK

1

I

Reset signal

RESET

RESETLOC1±

2

I

Reset-vector location pins

RESETLOC0

ROMEN

1

I

On-chip ROM enable ( 0 = disable, 1 = enable)

TCLK0

1

I / O

Timer 0 pin

TCLK1

1

I / O

Timer 1 pin

CLOCK ( 4 PINS)

X1

1

O

Crystal pin

X2 / CLKIN

1

I

Crystal / oscillator pin

H1

1

O

H1 clock

H3

1

O

H3 clock

POWER ( 70 PINS)

CVSS

15

I

Ground pins

DVSS

15

I

Ground pins

IVSS

6

I

Ground pins

DVDD

13

I

5-VDC supply pins

GADVDD

3

I

5-VDC supply pins

GDDVDD

3

I

5-VDC supply pins

LADVDD

3

I

5-VDC supply pins

LDDVDD

3

I

5-VDC supply pins

SUBS

1

I

Substrate pin ( tie to ground)