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TMS320C40

DIGITAL SIGNAL PROCESSOR

SPRS038 ± JANUARY 1996

H 3

(L)STRBx

(L)R / Wx	5
	4

(L)Ax

(L)Dx

(L)RDYx

8.1

(L)STATx

Figure 9. Memory-Read-Cycle Timing [(L)STRBx = 0]

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

TMS320C40

DIGITAL SIGNAL PROCESSOR

SPRS038 ± JANUARY 1996

H1
1	2
	2
(L)STRBx
3	9
(L)R / Wx
4	12
(L)Ax
10	11
(L)Dx
	8
(L)RDYx
	7

(L)STATx

Figure 10. Memory-Write-Cycle Timing [(L)STRBx = 0]

22	POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

TMS320C40

DIGITAL SIGNAL PROCESSOR

SPRS038 ± JANUARY 1996

-, and

-enable timing (see Figure 11)

(L)DE

(L)AE

(L)CEx

TMS320C40 - 40

TMS320C40 - 60

NO.

TMS320C40 - 50

UNIT

MIN

MAX

MIN

MAX

Delay time,

high to (L)D0 ± (L)D31 in the high-impedance

0²

15³

0²

15³

(L)DE

d(DEH - DZ)

state

td(DEL - DV)

Delay time,

low to (L)D0 ± (L)D31 valid

0²

(L)DE

Delay time,

high to (L)A0 ± (L)A30 in the high-impedance

td(AEH - AZ)

(L)AE

0²

15³

0²

15³

state

Delay time,

low to (L)A0 ± (L)A30 valid

0²

(L)AE

d(AEL - AV)

Delay time,

high to (L)R /

td(CEH - RWZ)

(L)CEx

W0, (L)R / W1 in the

0²

15³

0²

15³

high-impedance state

td(CEL - RWV)

Delay time,

low to (L)R /

0²

(L)CEx

W0, (L)R / W1 valid

Delay time,

high to

in the

td(CEH - SZ)

(L)CEx

(L)STRB0,

(L)STRB1

0²

15³

0²

15³

high-impedance state

td(CEL - SV)

Delay time,

low to

valid

0²

(L)CEx

(L)STRB0,

(L)STRB1

Delay time,

high to (L)PAGE0, (L)PAGE1 in the

0²

15³

0²

15³

(L)CEx

d(CEH - PAGEZ)

high-impedance state

td(CEL - PAGEV)

Delay time,

low to (L)PAGE0, (L)PAGE1 valid

0²

(L)CEx

This value is specified by design but not tested.

This value is characterized but not tested.

(L)DE

(L)Dx

Hi-Z

(L)AE

(L)Ax

Hi-Z

(L)CEx

(L)R /

Hi-Z

(L)STRBx

Hi-Z

(L)PAGEx

Hi-Z

Figure 11. (L)DE -, (L)AE -, and (L)CEx-Enable Timings

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

TMS320C40

DIGITAL SIGNAL PROCESSOR

SPRS038 ± JANUARY 1996

timing for (L)LOCK when executing LDFI or LDII (see Figure 12)

NO.				TMS320C40 - 40		TMS320C40 - 50	TMS320C40 - 60	UNIT

				MIN	MAX	MIN MAX	MIN MAX


1	td(H1L - LOCKL) Delay time, H1 low to		low		11	8	8	ns
		(L)LOCK

LDFI or LDII

External Access

(L)STRBx

(L)R / Wx

(L)Ax

(L)Dx

(L)RDYx

(L)LOCK

Figure 12. Timing for (L)LOCK When Executing LDFI or LDII

24	POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

TMS320C40

DIGITAL SIGNAL PROCESSOR

SPRS038 ± JANUARY 1996

timing for (L)LOCK when executing STFI or STII (see Figure 13)

NO.				TMS320C40 - 40		TMS320C40 - 50	TMS320C40 - 60	UNIT

				MIN	MAX	MIN MAX	MIN MAX


1	td(H1L - LOCKH) Delay time, H1 low to		high		11	8	8	ns
		(L)LOCK

STFI or STII

External Access

(L)STRBx

(L)R / Wx

(L)Ax

(L)Dx

(L)RDYx

(L)LOCK

Figure 13. Timing for (L)LOCK When Executing STFI or STII

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

TMS320C40

DIGITAL SIGNAL PROCESSOR

SPRS038 ± JANUARY 1996

timing for (L)LOCK when executing SIGI (see Figure 14)

NO.		TMS320C40 - 40 TMS320C40 - 50				TMS320C40 - 60		UNIT
NO.		MIN	MAX	MIN	MAX	MIN	MAX	UNIT
		MIN	MAX	MIN	MAX	MIN	MAX
1	td(H1L - LOCKL)	Delay time, H1 low to (L)LOCK low	11		8		8	ns
2	td(H1L - LOCKH)	Delay time, H1 low to (L)LOCK high	11		8		8
		H 3
		H1
		1	2

(L)LOCK

(L)R / Wx

(L)Ax

(L)Dx

(L)RDYx

(L)STATx

Figure 14. Timing for (L)LOCK When Executing SIGI

26	POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

TMS320C40

DIGITAL SIGNAL PROCESSOR

SPRS038 ± JANUARY 1996

timing for (L)PAGE0, (L)PAGE1 during memory access to a different page (see Figure 15)

		TMS320C40 - 40		TMS320C40 - 60
NO.		TMS320C40 - 50		TMS320C40 - 60		UNIT
		TMS320C40 - 50

		MIN	MAX	MIN	MAX
1 td(H1L - PAGEH)	Delay time, H1 low to (L)PAGEx high for access to different page	0	9	0	8	ns
2 td(H1L - PAGEL)	Delay time, H1 low to (L)PAGEx low for access to different page	0	9	0	8	ns
H1
(L)R / Wx
(L)STRBx

(L)RDYx

(L)PAGEx

(L)Dx

(L)Ax

(L)STATx

(L)STRB1 write to a different page

(L)STRB1 read from a different page

Figure 15. (L)PAGE0, (L)PAGE1 Timing Cycle, Memory Access to a Different Page

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

TMS320C40

DIGITAL SIGNAL PROCESSOR

SPRS038 ± JANUARY 1996

timing for the IIOFx when configured as an output (see Figure 16)

NO.		TMS320C40 - 40 TMS320C40 - 50				TMS320C40 - 60		UNIT
NO.		MIN	MAX	MIN	MAX	MIN	MAX	UNIT
		MIN	MAX	MIN	MAX	MIN	MAX
1 tv(H1L - IIOF)	H1 low to IIOFx valid		16		14		14	ns
	Fetch Load	Decode	Read		Execute
	Instruction	Decode	Read		Execute
H3
H1
FLAGx (IIF Register)							1 or 0
							1
IIOFx Pins

Figure 16. Timing for the IIOFx When Configured as an Output

28	POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

TMS320C40

DIGITAL SIGNAL PROCESSOR

					SPRS038 ± JANUARY 1996
timing of IIOFx changing from output to input mode (see Figure 17)
				TMS320C40 - 40	TMS320C40 - 60
NO.				TMS320C40 - 50	TMS320C40 - 60	UNIT
				TMS320C40 - 50

				MIN MAX	MIN MAX
1	th(H1L - IIOF)	Hold time, IIOFx after H1 low		14²	14²	ns
2	tsu(IIOF-H1L)	Setup time, IIOFx before H1 low		11	11	ns
3	th(H1L-IIOF)	Hold time, IIOFx after H1 low		0	0	ns
² This value is specified by design but not tested.
		Execute	Buffers Go	Synchronizer	Value on IIOF
		Load of IIF	From Output	Synchronizer	Value on IIOF
		Load of IIF	From Output	Delay	Seen in IIF
		Register	to Input	Delay	Seen in IIF
		Register	to Input
	H3
	H1
				2
	TYPEx			3
	TYPEx
	(IIF Register)
			1
	IIOFx	Output
	FLAGx		Data
	(IIF Register)		Data
	(IIF Register)		Sampled

Data

Seen

Figure 17. Change of IIOFx From Output to Input Mode

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

TMS320C40

DIGITAL SIGNAL PROCESSOR

SPRS038 ± JANUARY 1996

timing of IIOFx changing from input to output mode (see Figure 18)

NO.

TMS320C40 - 40

TMS320C40 - 50

TMS320C40 - 60

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

Delay time, H1 low to

switching from input to

td(H1L - IFIO)

IIOFx

output

Execution of

Load of IIF

TYPEx

(IIF Register)

IIOFx

Figure 18. Change of IIOFx From Input to Output Mode

RESET timing (see Figure 19)

NO.

TMS320C40 - 40

TMS320C40 - 50

TMS320C40 - 60

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

tsu(RESET-C1L)

Setup time for

before CLKIN low

tc(CI)²

RESET

2.1

td(CIH - H1H)

Delay time, CLKIN high to H1 high

2.2

td(CIH - H1L)

Delay time, CLKIN high to H1 low

Setup time for

high before H1 low

tsu(RESETH - H1L)

RESET

and after ten H1 clock cycles

4.1

td(CIH - H3L)

Delay time, CLKIN high to H3 low

4.2

td(CIH - H3H)

Delay time, CLKIN high to H3 high

Delay time, H1 high

(L)Dx

the

13³

d(H1H - DZ)

high-impedance state

td(H3H - AZ)

Delay time, H3 high

(L)Ax

the

9³

high-impedance state

td(H3H - CONTROLH)

Delay time, H3 high to control signals high

9³

[low for (L)PAGE]

9³

td(H1H - IACKH)

Delay time, H1 high to

IACK

high

Delay time,

low to asynchronous

td(RESETL - ASYNCH)

RESET

21³

reset signals in the high-impedance state

Delay time,

high to asynchronous

15³

RESET

d(RESETH - COMMH)

reset signals high

² tc(CI), the CLKIN period as shown in Figure 7 ³ This value is characterized but not tested.

30	POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

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