TMS320C6203B

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS086K – JANUARY 1999 – REVISED APRIL 2003

ASYNCHRONOUS MEMORY TIMING

timing requirements for asynchronous memory cycles†‡§¶ (see Figure 16 – Figure 19)

†To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.

‡RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are programmed via the EMIF CE space control registers.

§ P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.

¶ The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.

switching characteristics over recommended operating conditions for asynchronous memory cyclesद# (see Figure 16 РFigure 19)

‡ RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are programmed via the EMIF CE space control registers.

§ P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.

¶ The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.

#Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0], with the exception that CEx can stay active for an additional 7P ns following the end of the cycle.

TMS320C6203B

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS086K – JANUARY 1999 – REVISED APRIL 2003

ASYNCHRONOUS MEMORY TIMING (CONTINUED)

ED[31:0]

1

2

AOE

5

6

7

ARE

AWE

ARDY

†CEx stays active for seven minus the value of Read Hold cycles after the last access (DMA transfer or CPU access). For example, if read HOLD = 1, then CEx stays active for six more cycles. This does not affect performance, it merely reflects the EMIF’s overhead.

Figure 16. Asynchronous Memory Read Timing (ARDY Not Used)

8 10

9

ARE

AWE

11

ARDY

†CEx stays active for seven minus the value of Read Hold cycles after the last access (DMA transfer or CPU access). For example, if read HOLD = 1, then CEx stays active for six more cycles. This does not affect performance, it merely reflects the EMIF’s overhead.

Figure 17. Asynchronous Memory Read Timing (ARDY Used)

TMS320C6203B

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS086K – JANUARY 1999 – REVISED APRIL 2003

ASYNCHRONOUS MEMORY TIMING (CONTINUED)

AOE

15 ARE

16

14

AWE

ARDY

†If no write accesses are scheduled for the next cycle and write hold is set to 1 or greater, then CEx stays active for three cycles after the value of the programmed hold period. If write hold is set to 0, then CEx stays active for four more cycles. This does not affect performance, it merely reflects the EMIF’s overhead.

Figure 18. Asynchronous Memory Write Timing (ARDY Not Used)

AOE

ARE

17

18

19

AWE

11

ARDY

†If no write accesses are scheduled for the next cycle and write hold is set to 1 or greater, then CEx stays active for three cycles after the value of the programmed hold period. If write hold is set to 0, then CEx stays active for four more cycles. This does not affect performance, it merely reflects the EMIF’s overhead.

Figure 19. Asynchronous Memory Write Timing (ARDY Used)