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TMS320C6203B
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS086K – JANUARY 1999 – REVISED APRIL 2003
JTAG TEST-PORT TIMING
timing requirements for JTAG test port (see Figure 56)
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-250 |
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NO. |
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-300 |
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UNIT |
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MIN |
MAX |
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1 |
tc(TCK) |
Cycle time, TCK |
35 |
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ns |
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3 |
tsu(TDIV-TCKH) |
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Setup time, TDI/TMS/TRST |
valid before TCK high |
11 |
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ns |
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4 |
th(TCKH-TDIV) |
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9 |
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ns |
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Hold time, TDI/TMS/TRST |
valid after TCK high |
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switching characteristics over recommended operating conditions for JTAG test port (see Figure 56)
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-250 |
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NO. |
PARAMETER |
-300 |
UNIT |
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MIN |
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MAX |
2 |
td(TCKL-TDOV) Delay time, TCK low to TDO valid |
–4.5 |
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13.5 ns |
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1 |
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TCK |
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2 |
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2 |
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TDO |
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4 |
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3 |
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TDI/TMS/TRST
Figure 56. JTAG Test-Port Timing
96 |
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 |