TMS320C6203B

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS086K – JANUARY 1999 – REVISED APRIL 2003

EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING

timing requirements for asynchronous peripheral cycles†‡§¶ (see Figure 34–Figure 37)

†To ensure data setup time, simply program the strobe width wide enough. XRDY is internally synchronized. If XRDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, XRDY can be an asynchronous input.

‡RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are programmed via the XBUS XCE space control registers.

§ P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.

¶ The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use XRDY input to extend strobe width.

switching characteristics over recommended operating conditions for asynchronous peripheral cycles‡§¶# (see Figure 34–Figure 37)

‡ RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are programmed via the XBUS XCE space control registers.

§ P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.

¶ The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use XRDY input to extend strobe width.

#Select signals include: XCEx, XBE[3:0]/XA[5:2], XOE; and for writes, include XD[31:0], with the exception that XCEx can stay active for an additional 7P ns following the end of the cycle.

TMS320C6203B

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS086K – JANUARY 1999 – REVISED APRIL 2003

EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED)

† XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.

‡ XWE/XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses. § XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.

Figure 34. Expansion Bus Asynchronous Peripheral Read Timing (XRDY Not Used)

† XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.

‡ XWE/XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses. § XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.

Figure 35. Expansion Bus Asynchronous Peripheral Read Timing (XRDY Used)

† XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.

‡ XWE/XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses. § XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.

Figure 36. Expansion Bus Asynchronous Peripheral Write Timing (XRDY Not Used)

† XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.

‡ XWE/XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses. § XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.

Figure 37. Expansion Bus Asynchronous Peripheral Write Timing (XRDY Used)