TMS320C6203B
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS086K – JANUARY 1999 – REVISED APRIL 2003
EXPANSION BUS ASYNCHRONOUS HOST-PORT TIMING
timing requirements with external device as asynchronous bus master† (see Figure 43 and Figure 44)
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-250 |
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NO. |
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-300 |
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UNIT |
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MIN |
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MAX |
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1 |
tw(XCSL) |
Pulse duration, |
XCS |
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low |
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4P |
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ns |
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2 |
tw(XCSH) |
Pulse duration, |
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high |
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4P |
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ns |
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XCS |
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3 |
t |
Setup time, expansion bus select signals‡ |
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valid before |
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low |
1 |
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ns |
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XCS |
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su(XSEL-XCSL) |
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4 |
th(XCSL-XSEL) |
Hold time, expansion bus select signals‡ |
valid after |
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low |
3.4 |
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ns |
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XCS |
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10 |
th(XRYL-XCSL) |
Hold time, |
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low after XRDY low |
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P + 1.5 |
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ns |
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XCS |
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11 |
t |
Setup time, |
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1 |
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ns |
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XBE[3:0]/XA[5:2] valid before XCS high§ |
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su(XBEV-XCSH) |
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12 |
th(XCSH-XBEV) |
Hold time, |
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3 |
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ns |
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XBE[3:0]/XA[5:2] valid after XCS high§ |
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13 |
tsu(XDV-XCSH) |
Setup time, XDx valid before |
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high |
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1 |
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ns |
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XCS |
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14 |
th(XCSH-XDV) |
Hold time, XDx valid after |
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high |
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3 |
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ns |
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XCS |
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† P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡ Expansion bus select signals include XCNTL and XR/W.
§ XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
switching characteristics over recommended operating conditions with external device as asynchronous bus master† (see Figure 43 and Figure 44)
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-250 |
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NO. |
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PARAMETER |
-300 |
UNIT |
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MIN |
MAX |
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5 |
td(XCSL-XDLZ) |
Delay time, |
XCS |
low to XDx low impedance |
0 |
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ns |
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6 |
td(XCSH-XDIV) |
Delay time, |
XCS |
high to XDx invalid |
0 |
12 |
ns |
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7 |
td(XCSH-XDHZ) |
Delay time, |
XCS |
high to XDx high impedance |
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4P |
ns |
8 |
td(XRYL-XDV) |
Delay time, XRDY low to XDx valid |
–4 |
1.8 |
ns |
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9 |
td(XCSH-XRYH) |
Delay time, |
XCS |
high to XRDY high |
–1 |
12 |
ns |
† P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
78 |
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 |
TMS320C6203B
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS086K – JANUARY 1999 – REVISED APRIL 2003
EXPANSION BUS ASYNCHRONOUS HOST-PORT TIMING (CONTINUED)
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1 |
2 |
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1 |
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10 |
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10 |
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XCS |
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3 |
4 |
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3 |
4 |
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XCNTL |
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XBE[3:0]/XA[5:2]† |
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3 |
4 |
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3 |
4 |
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XR/W‡ |
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3 |
4 |
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3 |
4 |
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XR/W‡ |
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7 |
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7 |
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5 |
8 |
6 |
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5 |
8 |
6 |
XD[31:0] |
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Word |
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9 |
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9 |
XRDY |
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† XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
‡ XW/R input/output polarity selected at boot
Figure 43. External Device as Asynchronous Master—Read
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10 |
1 |
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2 |
10 |
XCS |
1 |
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3 |
3 |
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4 |
4 |
XCNTL |
11 |
11 |
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12 |
12 |
XBE[3:0]/XA[5:2]†
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3 |
3 |
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4 |
4 |
XR/W‡ |
3 |
3 |
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4 |
4 |
XR/W‡ |
13 |
13 |
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14 |
14 |
XD[31:0] |
wordWord |
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9 |
9 |
XRDY |
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† XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
‡ XW/R input/output polarity selected at boot
Figure 44. External Device as Asynchronous Master—Write
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 |
79 |