- •Table of Contents
- •REVISION HISTORY
- •GNZ, GLS, and GNY BGA packages (bottom view)
- •description
- •device characteristics
- •functional and CPU (DSP core) block diagram
- •CPU (DSP core) description
- •memory map summary
- •peripheral register descriptions
- •DMA synchronization events
- •interrupt sources and interrupt selector
- •signal groups description
- •Signal Descriptions
- •development support
- •Software Development Tools:
- •Hardware Development Tools:
- •device and development-support tool nomenclature
- •TMDX
- •TMDS
- •documentation support
- •clock PLL
- •power-supply sequencing
- •system-level design considerations
- •power-supply design considerations
- •IEEE 1149.1 JTAG compatibility statement
- •recommended operating conditions
- •PARAMETER MEASUREMENT INFORMATION
- •signal transition levels
- •timing parameters and board routing analysis
- •INPUT AND OUTPUT CLOCKS
- •ASYNCHRONOUS MEMORY TIMING
- •SYNCHRONOUS-BURST MEMORY TIMING
- •SYNCHRONOUS DRAM TIMING
- •RESET TIMING
- •EXTERNAL INTERRUPT TIMING
- •EXPANSION BUS SYNCHRONOUS FIFO TIMING
- •EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING
- •EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING
- •EXPANSION BUS ASYNCHRONOUS HOST-PORT TIMING
- •XHOLD/XHOLDA TIMING
- •MULTICHANNEL BUFFERED SERIAL PORT TIMING
- •timing requirements for FSR when GSYNC = 1 (see Figure 48)
- •DMAC, TIMER, POWER-DOWN TIMING
- •JTAG TEST-PORT TIMING
- •timing requirements for JTAG test port (see Figure 56)
- •MECHANICAL DATA
- •thermal resistance characteristics (S-PBGA package)
- •thermal resistance characteristics (S-PBGA package)
- •thermal resistance characteristics (S-PBGA package)
- •IMPORTANT NOTICE
TMS320C6203B
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS086K – JANUARY 1999 – REVISED APRIL 2003
DMAC, TIMER, POWER-DOWN TIMING
switching characteristics over recommended operating conditions for DMAC outputs† (see Figure 53)
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-250 |
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NO. |
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PARAMETER |
-300 |
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UNIT |
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MIN |
MAX |
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1 |
tw(DMACH) Pulse duration, DMAC high |
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2P–3 |
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ns |
† P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
1
DMAC[3:0]
Figure 53. DMAC Timing
timing requirements for timer inputs† (see Figure 54)
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-250 |
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NO. |
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-300 |
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UNIT |
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MIN |
MAX |
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1 |
tw(TINPH) |
Pulse duration, TINP high |
2P |
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ns |
2 |
tw(TINPL) |
Pulse duration, TINP low |
2P |
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ns |
† P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
switching characteristics over recommended operating conditions for timer outputs† (see Figure 54)
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-250 |
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NO. |
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PARAMETER |
-300 |
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UNIT |
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MIN |
MAX |
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3 |
tw(TOUTH) |
Pulse duration, TOUT high |
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2P–3 |
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ns |
4 |
tw(TOUTL) |
Pulse duration, TOUT low |
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2P–3 |
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ns |
† P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
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2 |
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1 |
TINPx |
4 |
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3
TOUTx
Figure 54. Timer Timing
94 |
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 |
TMS320C6203B
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS086K – JANUARY 1999 – REVISED APRIL 2003
DMAC, TIMER, POWER-DOWN TIMING (CONTINUED)
switching characteristics over recommended operating conditions for power-down outputs† (see Figure 55)
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-250 |
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NO. |
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PARAMETER |
-300 |
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UNIT |
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MIN |
MAX |
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1 |
tw(PDH) |
Pulse duration, PD high |
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2P |
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ns |
† P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
1
PD
Figure 55. Power-Down Timing
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 |
95 |