- •Table of Contents
- •REVISION HISTORY
- •GNZ, GLS, and GNY BGA packages (bottom view)
- •description
- •device characteristics
- •functional and CPU (DSP core) block diagram
- •CPU (DSP core) description
- •memory map summary
- •peripheral register descriptions
- •DMA synchronization events
- •interrupt sources and interrupt selector
- •signal groups description
- •Signal Descriptions
- •development support
- •Software Development Tools:
- •Hardware Development Tools:
- •device and development-support tool nomenclature
- •TMDX
- •TMDS
- •documentation support
- •clock PLL
- •power-supply sequencing
- •system-level design considerations
- •power-supply design considerations
- •IEEE 1149.1 JTAG compatibility statement
- •recommended operating conditions
- •PARAMETER MEASUREMENT INFORMATION
- •signal transition levels
- •timing parameters and board routing analysis
- •INPUT AND OUTPUT CLOCKS
- •ASYNCHRONOUS MEMORY TIMING
- •SYNCHRONOUS-BURST MEMORY TIMING
- •SYNCHRONOUS DRAM TIMING
- •RESET TIMING
- •EXTERNAL INTERRUPT TIMING
- •EXPANSION BUS SYNCHRONOUS FIFO TIMING
- •EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING
- •EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING
- •EXPANSION BUS ASYNCHRONOUS HOST-PORT TIMING
- •XHOLD/XHOLDA TIMING
- •MULTICHANNEL BUFFERED SERIAL PORT TIMING
- •timing requirements for FSR when GSYNC = 1 (see Figure 48)
- •DMAC, TIMER, POWER-DOWN TIMING
- •JTAG TEST-PORT TIMING
- •timing requirements for JTAG test port (see Figure 56)
- •MECHANICAL DATA
- •thermal resistance characteristics (S-PBGA package)
- •thermal resistance characteristics (S-PBGA package)
- •thermal resistance characteristics (S-PBGA package)
- •IMPORTANT NOTICE
TMS320C6203B
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS086K – JANUARY 1999 – REVISED APRIL 2003
XHOLD/XHOLDA TIMING
timing requirements for expansion bus arbitration (internal arbiter enabled)† (see Figure 45)
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3 |
toh(XHDAH-XHDH) Output hold time, XHOLD high after XHOLDA high |
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† P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
switching characteristics over recommended operating conditions for expansion bus arbitration (internal arbiter enabled)†‡ (see Figure 45)
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PARAMETER |
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1 |
td(XHDH-XBHZ) |
Delay time, XHOLD high to XBus high impedance |
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td(XBHZ-XHDAH) |
Delay time, XBus high impedance to XHOLDA high |
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2P |
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td(XHDL-XHDAL) |
Delay time, XHOLD low to XHOLDA low |
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td(XHDAL-XBLZ) |
Delay time, XHOLDA low to XBus low impedance |
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† P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. |
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‡ XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST. |
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§ All pending XBus transactions are allowed to complete before XHOLDA is asserted. |
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DSP Owns Bus |
External Requestor |
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XHOLD (input) |
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XHOLDA (output) |
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XBus† |
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C6203B |
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C6203B |
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† XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.
Figure 45. Expansion Bus Arbitration—Internal Arbiter Enabled
80 |
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 |
TMS320C6203B
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS086K – JANUARY 1999 – REVISED APRIL 2003
XHOLD/XHOLDA TIMING (CONTINUED)
switching characteristics over recommended operating conditions for expansion bus arbitration (internal arbiter disabled)† (see Figure 46)
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-250 |
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NO. |
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PARAMETER |
-300 |
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1 |
t |
Delay time, XHOLDA high to XBus low impedance‡ |
2P |
2P + 10 |
ns |
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d(XHDAH-XBLZ) |
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2 |
td(XBHZ-XHDL) |
Delay time, XBus high impedance to XHOLD low‡ |
0 |
2P |
ns |
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† P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. |
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‡ XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST. |
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XHOLD (output) |
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XHOLDA (input) |
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XBus† |
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C6203B |
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† XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.
Figure 46. Expansion Bus Arbitration—Internal Arbiter Disabled
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 |
81 |