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Аналіз обчислювальної похибки при виконанні базових операцій алгоритмів цифрової обробки сигналів. Обчислення математичних функцій роектування комп’ютерних засобів обробки сигналів та зображень Ваврук. Лаби для 13 групи / MAZ / MAZ-DOD-MAT-2012 / TMS320C6203.pdf

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TMS320C6203B

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS086K – JANUARY 1999 – REVISED APRIL 2003

SYNCHRONOUS DRAM TIMING

timing requirements for synchronous DRAM cycles for C6203B Rev. 2 (see Figure 22)

				REV. 2

NO.			-250		-300	UNIT
			MIN MAX		MIN MAX
7	tsu(EDV-CKO2H)	Setup time, read EDx valid before CLKOUT2 high	1.2		0.5	ns
8	th(CKO2H-EDV)	Hold time, read EDx valid after CLKOUT2 high	2.7		2	ns

switching characteristics over recommended operating conditions for synchronous DRAM cycles for C6203B Rev. 2†‡ (see Figure 22–Figure 27)

REV. 2

NO.

PARAMETER

-250

-300

UNIT

MIN

MAX

MIN

MAX

tosu(CEV-CKO2H)

Output setup time,

CEx

valid before CLKOUT2 high

P – 0.9

P + 0.6

toh(CKO2H-CEV)

Output hold time,

CEx

valid after CLKOUT2 high

P – 2.9

P – 1.8

tosu(BEV-CKO2H)

Output setup time,

BEx

valid before CLKOUT2 high

P – 0.9

P + 0.6

toh(CKO2H-BEIV)

Output hold time,

BEx

invalid after CLKOUT2 high

P – 2.9

P – 1.8

tosu(EAV-CKO2H)

Output setup time, EAx valid before CLKOUT2 high

P – 0.9

P + 0.6

toh(CKO2H-EAIV)

Output hold time, EAx invalid after CLKOUT2 high

P – 2.9

P – 1.8

tosu(CASV-CKO2H)

Output setup time,

SDCAS/SSADS valid before

P – 0.9

P + 0.6

CLKOUT2 high

toh(CKO2H-CASV)

Output hold time,

SDCAS/SSADS valid after CLKOUT2

P – 2.9

P – 1.8

high

tosu(EDV-CKO2H)

Output setup time, EDx valid before CLKOUT2 high§

P – 1.5

P + 0.6

toh(CKO2H-EDIV)

Output hold time, EDx invalid after CLKOUT2 high

P – 2.8

P – 1.8

tosu(WEV-CKO2H)

Output setup time,

SDWE/SSWE valid before

P – 0.9

P + 0.6

CLKOUT2 high

toh(CKO2H-WEV)

Output hold time,

SDWE/SSWE valid after CLKOUT2

P – 2.9

P – 1.8

high

tosu(SDA10V-CKO2H)

Output setup time, SDA10 valid before CLKOUT2 high

P – 0.9

P + 0.6

toh(CKO2H-SDA10IV)

Output hold time, SDA10 invalid after CLKOUT2 high

P – 2.9

P – 1.8

tosu(RASV-CKO2H)

Output setup time,

SDRAS/SSOE valid before

P – 0.9

P + 0.6

CLKOUT2 high

toh(CKO2H-RASV)

Output hold time,

SDRAS/SSOE valid after CLKOUT2

P – 2.9

P – 1.8

high

† P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.

‡ SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.

§For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate the ED enable time.

56	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6203B

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS086K – JANUARY 1999 – REVISED APRIL 2003

SYNCHRONOUS DRAM TIMING (CONTINUED)

timing requirements for synchronous DRAM cycles for C6203B Rev. 3 (see Figure 22)

					REV. 3
			C6203BGNY173-250		C6203BGNY173-300
			C6203BGNY173-250		C6203BGNY300-300
NO.			C6203BGNZ173-250		C6203BGNY300-300		C6203BGNY3E-300		UNIT
NO.			C6203BGNZ173-250		C6203BGNZ173-300		C6203BGNY3E-300		UNIT
			C6203BGNZA-250		C6203BGNZ173-300
			C6203BGNZA-250		C6203BGNZ300-300
					C6203BGNZ300-300
			MIN	MAX	MIN	MAX	MIN	MAX

		Setup time, read
7	tsu(EDV-CKO2H)	EDx valid before	1.3		0		0		ns
		CLKOUT2 high

		Hold time, read EDx
8	th(CKO2H-EDV)	valid after CLKOUT2	2.3		2.3		2.7		ns
		high

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6203B

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS086K – JANUARY 1999 – REVISED APRIL 2003

SYNCHRONOUS DRAM TIMING (CONTINUED)

switching characteristics over recommended operating conditions for synchronous DRAM cycles for C6203B Rev. 3†‡ (see Figure 22–Figure 27)

REV. 3

C6203BGNY173-250

C6203BGNY173-300

C6203BGNY300-300

NO.

PARAMETER

C6203BGNZ173-250

C6203BGNY3E-300

UNIT

C6203BGNZ173-300

C6203BGNZA-250

C6203BGNZ300-300

MIN

MAX

MIN

MAX

MIN

MAX

Output setup

tosu(CEV-CKO2H)

time, CEx valid

P – 1.7

P – 1

P – 1.5

before

CLKOUT2 high

Output hold

toh(CKO2H-CEV)

time, CEx valid

P – 3

P – 2.3

after CLKOUT2

high

Output setup

tosu(BEV-CKO2H)

time, BEx valid

P – 1.7

P – 1

P – 1.5

before

CLKOUT2 high

Output hold

toh(CKO2H-BEIV)

time, BEx

P – 3

P – 2.3

invalid after

CLKOUT2 high

Output setup

tosu(EAV-CKO2H)

time, EAx valid

P – 1.7

P – 1

P – 1.5

before

CLKOUT2 high

Output hold

toh(CKO2H-EAIV)

time, EAx

P – 3

P – 2.3

invalid after

CLKOUT2 high

Output setup

time,

tosu(CASV-CKO2H)

SDCAS/SSADS

P – 1.7

P – 1

P – 1.5

valid before

CLKOUT2 high

Output hold

time,

toh(CKO2H-CASV)

SDCAS

/SSADS

P – 3

P – 2.3

valid after

CLKOUT2 high

Output setup

time, EDx valid

tosu(EDV-CKO2H)

before

P – 2.3

P – 1.6

P – 1.5

CLKOUT2

high§

† P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.

‡ SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.

§For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate the ED enable time.

58	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6203B

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS086K – JANUARY 1999 – REVISED APRIL 2003

SYNCHRONOUS DRAM TIMING (CONTINUED)

switching characteristics over recommended operating conditions for synchronous DRAM cycles for C6203B Rev. 3†‡ (see Figure 22–Figure 27) (continued)

REV. 3

C6203BGNY173-250

C6203BGNY173-300

C6203BGNY300-300

NO.

PARAMETER

C6203BGNZ173-250

C6203BGNY3E-300

UNIT

C6203BGNZ173-300

C6203BGNZA-250

C6203BGNZ300-300

MIN

MAX

MIN

MAX

MIN

MAX

Output hold

toh(CKO2H-EDIV)

time, EDx

P – 2.7

P – 2

invalid after

CLKOUT2 high

Output setup

time,

tosu(WEV-CKO2H)

SDWE/SSWE

P – 1.7

P – 1

P – 1.5

valid before

CLKOUT2 high

Output hold

time,

toh(CKO2H-WEV)

SDWE/SSWE

P – 3

P – 2.3

valid after

CLKOUT2 high

Output setup

tosu(SDA10V-CKO2H)

time, SDA10

P – 1.7

P – 1

P – 1.5

valid before

CLKOUT2 high

Output hold

toh(CKO2H-SDA10IV)

time, SDA10

P – 3

P – 2.3

invalid after

CLKOUT2 high

Output setup

time,

tosu(RASV-CKO2H)

SDRAS

/SSOE

P – 1.7

P – 1

P – 1.5

valid before

CLKOUT2 high

Output hold

time,

toh(CKO2H-RASV)

SDRAS/SSOE

P – 3

P – 2.3

valid after

CLKOUT2 high

† P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.

‡ SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.

§For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate the ED enable time.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6203B

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS086K – JANUARY 1999 – REVISED APRIL 2003

SYNCHRONOUS DRAM TIMING (CONTINUED)

		READ	READ	READ
CLKOUT2
	1			2
CEx
		3	4
			4
BE[3:0]		BE1	BE2	BE3
	5	6
		6
EA[15:2]	CA1	CA2	CA3
				7	8
					8
ED[31:0]				D1	D2	D3
	15			16
SDA10
SDRAS/SSOE†
	9			10

SDCAS/SSADS†

SDWE/SSWE†

† SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.

Figure 22. Three SDRAM READ Commands

	WRITE	WRITE	WRITE
CLKOUT2
	1		2
			2
CEx
	3	4
		4
BE[3:0]	BE1	BE2	BE3
	5	6
		6
EA[15:2]	CA1	CA2	CA3
	11	12
		12
	D1	D2	D3
ED[31:0]	15		16
	15		16
SDA10
SDRAS/SSOE†
	9		10
SDCAS/SSADS†
	13		14
SDWE/SSWE†

† SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.

Figure 23. Three SDRAM WRT Commands

60	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6203B

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS086K – JANUARY 1999 – REVISED APRIL 2003

SYNCHRONOUS DRAM TIMING (CONTINUED)

	ACTV
CLKOUT2
	1
	2
CEx
BE[3:0]
	5
EA[15:2]	Bank Activate/Row Address
ED[31:0]
	15
SDA10	Row Address

SDRAS/SSOE†

SDCAS/SSADS†

SDWE/SSWE†

† SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.

Figure 24. SDRAM ACTV Command

DCAB

CLKOUT2

1 2

CEx

BE[3:0]

EA[15:2]

ED[31:0]

15 16

SDA10

17 18

SDRAS/SSOE†

SDCAS/SSADS†

SDWE/SSWE†

† SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.

Figure 25. SDRAM DCAB Command

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6203B

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS086K – JANUARY 1999 – REVISED APRIL 2003

SYNCHRONOUS DRAM TIMING (CONTINUED)

REFR

CLKOUT2

CEx

BE[3:0] EA[15:2] ED[31:0]

SDA10

SDRAS/SSOE†

SDCAS/SSADS†

SDWE/SSWE†

† SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.

Figure 26. SDRAM REFR Command

MRS

CLKOUT2

1 2

CEx

BE[3:0]

	5	6
EA[15:2]	MRS Value

ED[31:0]

SDA10

17 18

SDRAS/SSOE†

9 10

SDCAS/SSADS†

13 14

SDWE/SSWE†

† SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.

Figure 27. SDRAM MRS Command

62	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6203B

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS086K – JANUARY 1999 – REVISED APRIL 2003

HOLD/HOLDA TIMING

timing requirements for the

HOLD/HOLDA cycles† (see Figure 28)

-250

NO.

-300

UNIT

MIN

MAX

toh(HOLDAL-HOLDL) Output hold time,

low after

low

HOLD

HOLDA

† P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.

switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles†‡ (see Figure 28)

									-250
NO.				PARAMETER					-300		UNIT

									MIN	MAX

1	td(HOLDL-EMHZ)	Delay time,		low to EMIF Bus high impedance					3P	§	ns
			HOLD
2	td(EMHZ-HOLDAL)	Delay time, EMIF Bus high impedance to						low	0	2P	ns
						HOLDA
4	td(HOLDH-EMLZ)	Delay time,		high to EMIF Bus low impedance					3P	7P	ns
			HOLD
5	td(EMLZ-HOLDAH)	Delay time, EMIF Bus low impedance to					high		0	2P	ns
					HOLDA

† P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.

‡ EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.

§All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst case for this is an asynchronous read or write with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.

	DSP Owns Bus	External Requestor	DSP Owns Bus
	DSP Owns Bus	Owns Bus	DSP Owns Bus
		Owns Bus
		3
HOLD
	2		5
HOLDA
EMIF Bus†	1		4
EMIF Bus†	C6203B		C6203B

† EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.

Figure 28. HOLD/HOLDA Timing

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

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