TMS320C6203B
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS086K – JANUARY 1999 – REVISED APRIL 2003
EXTERNAL INTERRUPT TIMING
timing requirements for interrupt response cycles† (see Figure 30)
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-250 |
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NO. |
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-300 |
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UNIT |
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MIN |
MAX |
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2 |
tw(ILOW) |
Width of the interrupt pulse low |
2P |
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ns |
3 |
tw(IHIGH) |
Width of the interrupt pulse high |
2P |
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ns |
† P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
switching characteristics over recommended operating conditions during interrupt response cycles†‡ (see Figure 30)
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-250 |
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NO. |
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PARAMETER |
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-300 |
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UNIT |
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MIN |
MAX |
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1 |
tR(EINTH – IACKH) |
Response time, EXT_INTx high to IACK high |
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9P |
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ns |
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4 |
td(CKO2L-IACKV) |
Delay time, CLKOUT2 low to IACK valid |
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–1.5 |
10 |
ns |
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5 |
td(CKO2L-INUMV) |
Delay time, CLKOUT2 low to INUMx valid |
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–2.0 |
10 |
ns |
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6 |
td(CKO2L-INUMIV) |
Delay time, CLKOUT2 low to INUMx invalid |
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–2.0 |
10 |
ns |
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† P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns. |
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‡ When CLKOUT2 is in half (1/2) mode (see CLKOUT2 in Signal Descriptions table), timings are based on falling edges . |
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1 |
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CLKOUT2 (1/2) |
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2 |
3 |
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EXT_INTx, NMI |
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Intr Flag |
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4 |
4 |
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IACK |
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5 |
6 |
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INUMx |
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Interrupt Number |
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Figure 30. Interrupt Timing
66 |
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 |