TMS320C6203B
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS086K – JANUARY 1999 – REVISED APRIL 2003
EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING
timing requirements with external device as bus master (see Figure 38 and Figure 39)
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REV. 2 |
REV. 3 |
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NO. |
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-250 |
-250 |
UNIT |
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-300 |
-300 |
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MIN MAX |
MIN |
MAX |
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1 |
tsu(XCSV-XCKIH) |
Setup time, |
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valid before XCLKIN high |
3.5 |
3.5 |
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ns |
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XCS |
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2 |
th(XCKIH-XCS) |
Hold time, |
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valid after XCLKIN high |
2.8 |
2.8 |
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ns |
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XCS |
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3 |
tsu(XAS-XCKIH) |
Setup time, |
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valid before XCLKIN high |
3.5 |
3.5 |
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ns |
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XAS |
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4 |
th(XCKIH-XAS) |
Hold time, |
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valid after XCLKIN high |
2.8 |
2.8 |
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XAS |
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5 |
tsu(XCTL-XCKIH) |
Setup time, XCNTL valid before XCLKIN high |
3.5 |
3.5 |
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ns |
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6 |
th(XCKIH-XCTL) |
Hold time, XCNTL valid after XCLKIN high |
2.8 |
2.8 |
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ns |
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7 |
tsu(XWR-XCKIH) |
Setup time, XW/R valid before XCLKIN high† |
3.5 |
3.5 |
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ns |
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8 |
th(XCKIH-XWR) |
Hold time, XW/R valid after XCLKIN high† |
2.8 |
2.8 |
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ns |
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9 |
tsu(XBLTV-XCKIH) |
Setup time, XBLAST valid before XCLKIN high‡ |
3.5 |
3.5 |
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ns |
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10 |
t |
Hold time, XBLAST valid after XCLKIN high‡ |
2.8 |
2.8 |
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ns |
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h(XCKIH-XBLTV) |
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16 |
tsu(XBEV-XCKIH) |
Setup time, |
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3.5 |
3.5 |
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XBE[3:0]/XA[5:2] valid before XCLKIN high§ |
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17 |
t |
Hold time, |
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2.8 |
2.8 |
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XBE[3:0]/XA[5:2] valid after XCLKIN high§ |
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h(XCKIH-XBEV) |
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18 |
tsu(XD-XCKIH) |
Setup time, XDx valid before XCLKIN high |
3.5 |
3.5 |
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ns |
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19 |
th(XCKIH-XD) |
Hold time, XDx valid after XCLKIN high |
2.8 |
2.8 |
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ns |
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† XW/R input/output polarity selected at boot.
‡ XBLAST input polarity selected at boot
§ XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
switching characteristics over recommended operating conditions with external device as bus master¶ (see Figure 38 and Figure 39)
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REV. 2 |
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REV. 3 |
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NO. |
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PARAMETER |
-250 |
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-250 |
UNIT |
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-300 |
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-300 |
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MIN |
MAX |
MIN |
MAX |
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11 |
td(XCKIH-XDLZ) |
Delay time, XCLKIN high to XDx low impedance |
0 |
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0 |
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ns |
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12 |
td(XCKIH-XDV) |
Delay time, XCLKIN high to XDx valid |
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16.5 |
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4P – 0.5 |
ns |
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13 |
td(XCKIH-XDIV) |
Delay time, XCLKIN high to XDx invalid |
5 |
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3 |
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ns |
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14 |
td(XCKIH-XDHZ) |
Delay time, XCLKIN high to XDx high impedance |
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4P |
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4P |
ns |
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15 |
td(XCKIH-XRY) |
Delay time, XCLKIN high to XRDY invalid# |
5 |
16.5 |
3 |
4P – 0.5 |
ns |
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20 |
td(XCKIH-XRYLZ) |
Delay time, XCLKIN high to XRDY low impedance |
5 |
16.5 |
3 |
4P – 0.5 |
ns |
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21 |
t |
Delay time, XCLKIN high to XRDY high impedance# |
2P + 5 3P + 16.5 |
2P + 3 |
7P – 0.5 |
ns |
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d(XCKIH-XRYHZ) |
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¶ P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
# XRDY operates as active-low ready input/output during host-port accesses.
72 |
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 |
TMS320C6203B
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS086K – JANUARY 1999 – REVISED APRIL 2003
EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED)
XCLKIN
1 |
2 |
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XCS |
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3 |
4 |
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XAS |
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5 |
6 |
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XCNTL |
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7 |
8 |
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XW/R† |
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7 |
8 |
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XW/R† |
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XBE[3:0]/XA[5:2]‡ |
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9 |
10 |
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XBLAST§ |
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9 |
10 |
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XBLAST§ |
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12 |
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13 |
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11 |
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14 |
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XD[31:0] |
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D1 |
D2 |
D3 |
D4 |
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20 |
15 |
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21 |
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15 |
XRDY¶
† XW/R input/output polarity selected at boot
‡ XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. § XBLAST input polarity selected at boot
¶ XRDY operates as active-low ready input/output during host-port accesses.
Figure 38. External Host as Bus Master—Read
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 |
73 |
TMS320C6203B
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS086K – JANUARY 1999 – REVISED APRIL 2003
EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED)
XCLKIN |
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1 |
2 |
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XCS |
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3 |
4 |
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XAS |
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5 |
6 |
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XCNTL |
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7 |
8 |
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XW/R† |
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7 |
8 |
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XW/R† |
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16 |
17 |
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XBE[3:0]/XA[5:2]‡ |
XBE1 |
XBE2 |
XBE3 |
XBE4 |
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9 |
10 |
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XBLAST§ |
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9 |
10 |
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XBLAST§ |
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19 |
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18 |
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XD[31:0] |
D1 |
D2 |
D3 |
D4 |
20 |
15 |
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21 |
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15 |
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XRDY¶ |
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† XW/R input/output polarity selected at boot |
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‡ XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. § XBLAST input polarity selected at boot
¶ XRDY operates as active-low ready input/output during host-port accesses.
Figure 39. External Host as Bus Master—Write
74 |
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 |
TMS320C6203B
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS086K – JANUARY 1999 – REVISED APRIL 2003
EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED)
timing requirements with C62x as bus master (see Figure 40, Figure 41, and Figure 42)
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REV. 2 |
REV. 3 |
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NO. |
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-250 |
-250 |
UNIT |
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-300 |
-300 |
|||
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MIN MAX |
MIN |
MAX |
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9 |
tsu(XDV-XCKIH) |
Setup time, XDx valid before XCLKIN high |
3.5 |
3.5 |
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ns |
10 |
th(XCKIH-XDV) |
Hold time, XDx valid after XCLKIN high |
2.8 |
2.8 |
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ns |
11 |
t |
Setup time, XRDY valid before XCLKIN high† |
3.5 |
3.5 |
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ns |
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su(XRY-XCKIH) |
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12 |
th(XCKIH-XRY) |
Hold time, XRDY valid after XCLKIN high† |
2.8 |
2.8 |
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ns |
14 |
tsu(XBFF-XCKIH) |
Setup time, XBOFF valid before XCLKIN high |
3.5 |
3.5 |
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ns |
15 |
th(XCKIH-XBFF) |
Hold time, XBOFF valid after XCLKIN high |
2.8 |
2.8 |
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ns |
† XRDY operates as active-low ready input/output during host-port accesses.
switching characteristics over recommended operating conditions with C62x as bus master‡
(see Figure 40, Figure 41, and Figure 42)
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REV. 2 |
REV. 3 |
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NO. |
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PARAMETER |
-250 |
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-250 |
UNIT |
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-300 |
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-300 |
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MIN |
MAX |
MIN |
MAX |
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1 |
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td(XCKIH-XASV) |
Delay time, XCLKIN high to |
XAS |
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valid |
5 |
16.5 |
3 |
4P – 0.5 |
ns |
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2 |
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t |
Delay time, XCLKIN high to XW/R valid§ |
5 |
16.5 |
3 |
4P – 0.5 |
ns |
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d(XCKIH-XWRV) |
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3 |
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td(XCKIH-XBLTV) |
Delay time, XCLKIN high to XBLAST valid¶ |
5 |
16.5 |
3 |
4P – 0.5 |
ns |
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4 |
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td(XCKIH-XBEV) |
Delay time, XCLKIN high to |
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5 |
16.5 |
3 |
4P – 0.5 |
ns |
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XBE[3:0]/XA[5:2] valid# |
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5 |
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td(XCKIH-XDLZ) |
Delay time, XCLKIN high to XDx low impedance |
0 |
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0 |
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ns |
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6 |
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td(XCKIH-XDV) |
Delay time, XCLKIN high to XDx valid |
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16.5 |
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4P – 0.5 |
ns |
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7 |
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td(XCKIH-XDIV) |
Delay time, XCLKIN high to XDx invalid |
5 |
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3 |
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ns |
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8 |
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td(XCKIH-XDHZ) |
Delay time, XCLKIN high to XDx high impedance |
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4P |
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4P |
ns |
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13 |
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td(XCKIH-XWTV) |
Delay time, XCLKIN high to |
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5 |
16.5 |
3 |
4P – 0.5 |
ns |
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XWE/XWAIT valid|| |
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‡ |
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. |
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§ XW/R input/output polarity selected at boot. |
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¶ |
XBLAST output polarity is always active low. |
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# XBE[3:0]/XA[5:2] operate as byte-enables |
XBE[3:0] |
during host-port accesses. |
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|| |
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XWE/XWAIT operates as XWAIT output signal during host-port accesses. |
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 |
75 |
TMS320C6203B
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS086K – JANUARY 1999 – REVISED APRIL 2003
EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED)
XCLKIN
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1 |
1 |
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XAS |
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XW/R† |
2 |
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2 |
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XW/R† |
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3 |
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3 |
XBLAST‡ |
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XBE[3:0]/XA[5:2]§ |
4 |
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4 |
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BE |
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5 |
7 |
9 |
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6 |
8 |
10 |
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XD[31:0] |
AD |
D1 |
D2 |
D3 |
D4 |
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11 |
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12 |
XRDY |
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13 |
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13 |
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XWE/XWAIT¶ |
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† XW/R input/output polarity selected at boot |
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‡ XBLAST output polarity is always active low. |
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§ XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. |
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¶ XWE/XWAIT operates as XWAIT output signal during host-port accesses. |
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Figure 40. C62x as Bus Master—Read |
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XCLKIN |
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1 |
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1 |
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XAS |
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XW/R† |
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XW/R† |
2 |
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2 |
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3 |
XBLAST‡ |
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3 |
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4 |
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4 |
XBE[3:0]/XA[5:2]§ |
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6 |
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7 |
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8 |
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5 |
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XD[31:0] |
Addr |
D1 |
D2 |
D3 |
D4 |
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11 |
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12 |
XRDY |
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13 |
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13 |
XWE/XWAIT¶ |
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† XW/R input/output polarity selected at boot |
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‡ XBLAST output polarity is always active low. |
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§ XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. |
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¶ XWE/XWAIT operates as XWAIT output signal during host-port accesses. |
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Figure 41. C62x as Bus Master—Write
76 |
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 |
TMS320C6203B
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS086K – JANUARY 1999 – REVISED APRIL 2003
EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED)
XCLKIN |
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1 |
1 |
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XAS |
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XW/R† |
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2 |
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2 |
XW/R† |
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XBLAST‡ |
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4 |
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4 |
XBE[3:0]/XA[5:2]§ |
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6 |
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7 |
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5 |
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8 |
Addr |
D1 |
D2 |
XD[31:0] |
11 |
12 |
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XRDY |
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15 |
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XBOFF |
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14 |
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XHOLD¶
XHOLDA¶
XHOLD#
XHOLDA#
† XW/R input/output polarity selected at boot
‡ XBLAST output polarity is always active low.
§ XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. ¶ Internal arbiter enabled
# Internal arbiter disabled
|| This diagram illustrates XBOFF timing. Bus arbitration timing is shown in Figure 45 and Figure 46.
Figure 42. C62x as Bus Master—XBOFF Operation||
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 |
77 |