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Аналіз обчислювальної похибки при виконанні базових операцій алгоритмів цифрової обробки сигналів. Обчислення математичних функцій роектування комп’ютерних засобів обробки сигналів та зображень Ваврук. Лаби для 13 групи / MAZ / MAZ-DOD-MAT-2012 / TMS320C6203.pdf

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TMS320C6203B

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS086K – JANUARY 1999 – REVISED APRIL 2003

EXPANSION BUS SYNCHRONOUS FIFO TIMING

timing requirements for synchronous FIFO interface (see Figure 31, Figure 32, and Figure 33)

			-250
NO.			-300		UNIT
NO.					UNIT
			MIN	MAX

5	tsu(XDV-XFCKH)	Setup time, read XDx valid before XFCLK high	3		ns
6	th(XFCKH-XDV)	Hold time, read XDx valid after XFCLK high	2.5		ns

switching characteristics over recommended operating conditions for synchronous FIFO interface (see Figure 31, Figure 32, and Figure 33)

-250

NO.

PARAMETER

-300

UNIT

MIN

MAX

td(XFCKH-XCEV)

Delay time, XFCLK high to

valid

1.5

5.5

XCEx

td(XFCKH-XAV)

Delay time, XFCLK high to

1.5

5.5

XBE[3:0]/XA[5:2] valid†

td(XFCKH-XOEV)

Delay time, XFCLK high to

valid

1.5

5.5

XOE

td(XFCKH-XREV)

Delay time, XFCLK high to

valid

1.5

5.5

XRE

Delay time, XFCLK high to

1.5

5.5

XWE/XWAIT‡ valid

d(XFCKH-XWEV)

td(XFCKH-XDV)

Delay time, XFCLK high to XDx valid

td(XFCKH-XDIV)

Delay time, XFCLK high to XDx invalid

1.5

†

/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses.

XBE[3:0]

‡

XWE

/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses.

XFCLK

†

XCE3

XA1

XA2

XA3

XA4

XBE[3:0]/XA[5:2]‡

XOE

XRE

XWE/XWAIT§

XD[31:0]

† FIFO read (glueless) mode only available in XCE3.

‡ XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses. § XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses.

Figure 31. FIFO Read Timing (Glueless Read Mode)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6203B

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS086K – JANUARY 1999 – REVISED APRIL 2003

EXPANSION BUS SYNCHRONOUS FIFO TIMING (CONTINUED)

XFCLK
	1				1
XCEx
	2				2
XBE[3:0]/XA[5:2]†	XA1	XA2	XA3		XA4
	3				3
XOE
	4				4
XRE
XWE/XWAIT‡			6
			6
		5
XD[31:0]		D1	D2	D3	D4
† XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses.
‡ XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses.
	Figure 32. FIFO Read Timing
XFCLK
		1			1
XCEx
		2			2
XBE[3:0]/XA[5:2]†		XA1	XA2	XA3	XA4
XOE
XRE
		7			7
XWE/XWAIT‡
					9
		8
XD[31:0]		D1	D2	D3	D4

† XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses.

‡ XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses.

Figure 33. FIFO Write Timing

68	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

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