TMS320C6678

 

 

 

 

 

Multicore Fixed and Floating-Point Digital Signal Processor

 

www.ti.com

 

 

 

 

SPRS691—November 2010

 

 

 

 

 

 

 

Table 2-2

Memory Map Summary for TMS320C6678 (Part 7 of 7)

 

 

 

 

 

 

 

 

 

Address

 

 

 

 

Start

 

End

Bytes

 

Description

 

21000100

 

213FFFFF

4M-256

 

Reserved

 

 

 

 

 

 

 

 

21400000

 

214003FF

1K

 

HyperLink Config

 

 

 

 

 

 

 

 

21400400

 

217FFFFF

4M-1K

 

Reserved

 

 

 

 

 

 

 

 

21800000

 

21807FFF

32K

 

PCIe Config

 

 

 

 

 

 

 

 

21808000

 

33FFFFFF

296M-32K

 

Reserved

 

 

 

 

 

 

 

 

34000000

 

341FFFFF

2M

 

Queue Manager Subsystem Data

 

 

 

 

 

 

 

 

34200000

 

3FFFFFFF

190M

 

Reserved

INFORMATION

 

 

 

 

 

 

40000000

 

4FFFFFFF

256M

 

HyperLink data

 

 

 

 

 

 

 

 

 

 

50000000

 

5FFFFFFF

256M

 

Reserved

 

 

 

 

 

 

 

 

60000000

 

6FFFFFFF

256M

 

PCIe Data

 

 

 

 

 

 

 

 

70000000

 

73FFFFFF

64M

 

EMIF16 CS2 Data NAND Memory

 

 

 

 

 

 

 

 

74000000

 

77FFFFFF

64M

 

EMIF16 CS3 Data NAND Memory

 

 

 

 

 

 

 

 

78000000

 

7BFFFFFF

64M

 

EMIF16 CS4 Data NOR Memory

 

 

 

 

 

 

 

 

7C000000

 

7FFFFFFF

64M

 

EMIF16 CS5 Data SRAM Memory

 

 

 

 

 

 

 

 

80000000

 

8FFFFFFF

256M

 

DDR3_ Data

 

 

 

 

 

 

 

 

90000000

 

9FFFFFFF

256M

 

DDR3_ Data

 

 

 

 

 

 

 

ADVANCE

A0000000

 

AFFFFFFF

256M

 

DDR3_ Data

 

 

 

 

 

 

B0000000

 

BFFFFFFF

256M

 

DDR3_ Data

 

 

 

 

 

 

 

 

 

 

C0000000

 

CFFFFFFF

256M

 

DDR3_ Data

 

 

 

 

 

 

 

 

D0000000

 

DFFFFFFF

256M

 

DDR3_ Data

 

 

 

 

 

 

 

 

E0000000

 

EFFFFFFF

256M

 

DDR3_ Data

 

 

 

 

 

 

 

 

F0000000

 

FFFFFFFF

256M

 

DDR3_ Data

 

 

 

 

 

 

 

End of Table 2-2

 

 

 

 

 

 

 

 

 

 

 

2.4 Boot Sequence

The boot sequence is a process by which the DSP's internal memory is loaded with program and data sections. The DSP's internal registers are programmed with predetermined values. The boot sequence is started automatically after each power-on reset, warm reset, and system reset. A local reset to an individual C66x CorePac should not affect the state of the hardware boot controller on the device. For more details on the initiators of the resets, see section ‘‘Reset Controller’’.

The C6678 supports several boot processes that begins execution at the ROM base address, which contains the bootloader code necessary to support various device boot modes. The boot processes are software-driven and use the BOOTMODE[12:0] device configuration inputs to determine the software configuration that must be completed. For more details on Boot Sequence see the Bootloader for the C66x DSP User Guide (literature number SPRUGY5).

Copyright 2010 Texas Instruments Incorporated

Device Overview

25

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