TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
www.ti.com |
SPRS691—November 2010 |
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3 Device Configuration
On the TMS320C6678 device, certain device configurations like boot mode and endianess, are selected at device power-on reset. The status of the peripherals (enabled/disabled) is determined after device power-on reset. By default, the peripherals on the device are disabled and need to be enabled by software before being used.
3.1 Device Configuration at Device Reset
Table 3-1 describes the device configuration pins. The logic level is latched at power-on reset to determine the device configuration. The logic level on the device configuration pins can be set by using external pullup/pulldown resistors or by using some control device (e.g., FPGA/CPLD) to intelligently drive these pins. When using a control device, care should be taken to ensure there is no contention on the lines when the device is out of reset. The device configuration pins are sampled during power-on reset and are driven after the reset is removed. To avoid contention, the control device must stop driving the device configuration pins of the DSP.
Note—If a configuration pin must be routed out from the device and it is not driven (Hi-Z state), the internal pullup/pulldown (IPU/IPD) resistor should not be relied upon. TI recommends the use of an external pullup/pulldown resistor. For more detailed information on pullup/pulldown resistors and situations in which external pullup/pulldown resistors are required, see Section 3.4 ‘‘Pullup/Pulldown Resistors’’ on page 80.
Table 3-1 |
TMS320C6678 Device Configuration Pins |
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Configuration Pin |
Pin No. |
IPD/IPU (1) |
Functional Description |
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LENDIAN(1) |
(2) |
H25 |
IPU |
Device endian mode (LENDIAN). |
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0 |
= Device operates in big endian mode |
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1 |
= Device operates in little endian mode |
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BOOTMODE[12:0] (1) (2) |
J28, J29, J26, J25, |
IPD |
Method of boot. |
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J27, J24, K27, K28, |
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Some pins may not be used by bootloader and can be used as general purpose config |
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K26, K29, L28, L29, |
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pins. Refer to the Bootloader for the C66x DSP User Guide (literature number SPRUGY5) for |
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K25 |
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how to determine the device enumeration ID value. |
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PCIESSMODE[1:0] (1) (2) |
L27, K24 |
IPD |
PCIe Subsystem mode selection. |
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00 = PCIe in end point mode |
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01 = PCIe legacy end point (no support for MSI) |
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10 = PCIe in root complex mode |
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11 = Reserved |
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PCIESSEN (1) (2) |
L24 |
IPD |
PCIe subsystem enable/disable. |
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0 |
= PCIE Subsystem is disabled |
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1 |
= PCIE Subsystem is enabled |
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PACLKSEL(1) |
AE4 |
IPD |
Packet accelerator subsystem clock select. |
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0 |
= SYSCLK / ALTCORECLK (controlled by CORECLKSEL pin) is used as the input to PA_SS |
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PLL |
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1 |
= PASSCLK is used as the input to PASS PLL |
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End of Table 3-1 |
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1 Internal 100-μA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩresistor can be used to oppose the IPD/IPU. For more detailed information on pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see Section 3.4 ‘‘Pullup/Pulldown Resistors’’ on page 80.
2 These signal names are the secondary functions of these pins.
3.2 Peripheral Selection After Device Reset
Several of the peripherals on the TMS320C6678 are controlled by the Power Sleep Controller (PSC). By default, the PCIe, SRIO, and HyperLink are held in reset and clock-gated. The memories in these modules are also in a low-leakage sleep mode. Software is required to turn these memories on. Then, the software enables the modules (turns on clocks and de-asserts reset) before these modules can be used.
ADVANCE INFORMATION
Copyright 2010 Texas Instruments Incorporated |
Device Configuration |
61 |