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Аналіз обчислювальної похибки при виконанні базових операцій алгоритмів цифрової обробки сигналів. Обчислення математичних функцій роектування комп’ютерних засобів обробки сигналів та зображень Ваврук. Лаби для 13 групи / MAZ / MAZ-DOD-MAT-2012 / tms320c6678.pdf

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TMS320C6678

Multicore Fixed and Floating-Point Digital Signal Processor

SPRS691—November 2010

www.ti.com

Table 7-4

-Controlled Power Sequencing — IO Before Core

POR

Time

System State

Begin Power Stabilization Phase

• DVDD18 (1.8 V) supply is ramped up followed coincidentally by HHV (1.8 V).

• Since

is low all the core logic having async reset (created from POR) are put into reset state once the core supply ramps.

must

POR

remain low through Power Stabilization Phase.

• Filtered versions of 1.8V can ramp simultaneously with DVDD18.

• RESETSTAT is driven low once the DVDD18 supply is available.

• All input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin before

DVDD18 could cause damage to the device.

t2a

•

and

may be driven high anytime after DVDD18 is at a valid level. In a

-controlled boot both

and

RESETFULL

RESET

POR

RESETFULL

RESET

ADVANCE

must be high before POR is driven high.

t3b

• Once CVDD is valid the clock drivers should be enabled. Although the clock inputs are not necessary at this time they should either be

t2b

• CVDD (core AVS) ramps up.

t3a

• CVDD1 (core constant) ramps at the same time or following CVDD. Although ramping CVDD1 and CVDD simultaneously is permitted the

voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage.

• The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 (core constant) should trail CVDD

(core AVS) as this will ensure that the WLs in the memories are turned off and there is no current through the memory bit cells. If,

however, CVDD1 (core constant) ramps up before CVDD (core AVS) then the worst case current could be on the order of twice the

specified draw of CVDD1.

INFORMATION

driven with a valid clock or held is a static state with one leg high and one leg low.

• The rising edge of the POR will remove the reset to the efuse farm allowing the scan to begin.

t3c

• The DDRCLK and REFCLK may begin to toggle anytime between when CVDD is at a valid level and the setup time before POR goes high

specified by t7.

• DVDD15 (1.5 V) supply is ramped up following CVDD1.

• POR must continue to remain low for at least 100 μs after power has stabilized.

End Power Stabilization Phase

Begin Device Initialization

• Device initialization requires 500 REFCLK periods after the Power Stabilization Phase. The maximum clock period is 33.33 nsec so a delay

of an additional 16 μs is required before a rising edge of POR. The clock must be active during the entire 16 μs.

•

must remain low.

POR

• Once device initialization and the efuse farm scan are complete, the

signal is driven high. This delay will be 10000 to 50000

RESETSTAT

clock cycles.

End Device Initialization Phase

End of Table 7-4

7.3.1.2 RESETFULL-Controlled Device Initialization

The timing diagrams in the figures below show the power sequencing and reset control of the device when RESETFULL is used to extend device initialization. In this mode, POR may be removed after the power has been stable for the required 100 μsec, but RESETFULL may be held low until the device initialization requirements have been met. On the rising edge of POR, the HHV signal will go inactive.

Note—REFCLK must always be active before POR can be removed.

7.3.1.2.1 Core-Before-IO Power Sequencing

104 TMS320C6678 Peripheral Information and Electrical Specifications

TMS320C6678

Multicore Fixed and Floating-Point Digital Signal Processor

www.ti.com	SPRS691—November 2010

The timing diagram for core-before-IO power sequencing is shown in Figure 7-7 and defined in Table 7-5.

Figure 7-7 RESETFULL-Controlled Device Initialization — Core Before IO

	Power Stabilization Phase			Chip Initialization Phase
PORz				t7
				t7
RESETFULLz
RESETz
	t1
CVDD(core AVS)		t4b	t5
			t5
	t2a
CVDD1 (core constant)		t3	t6
			t6

D VD D18 (1.8V)	t2b	t4a
D VD D18 (1.8V)
				t8
DVDD15 (1.5V)			t2c
REFCLKP&N
DDRCLKP&N
RESETSTATz
	RESETFULLz Controlled Reset Sequencing			– Core before IO

Table 7-5

RESETFULL-Controlled Device Initialization — Core Before IO (Part 1 of 2)

Time

System State

Begin Power Stabilization Phase

• CVDD (core AVS) ramps up.

•

must be held low through the power stabilization phase. Because

is low, all the core logic that has async reset (created from

POR

POR) is put into the reset state.

t2a

• CVDD1 (core constant) ramps at the same time or shortly following CVDD. Although ramping CVDD1 and CVDD simultaneously is

permitted, the voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage.

• The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 (core constant) should trail CVDD

(core AVS) as this will ensure that the WLs in the memories are turned off and there is no current through the memory bit cells. If,

however, CVDD1 (core constant) ramps up before CVDD (core AVS), then the worst-case current could be on the order of twice the

specified draw of CVDD1.

t2b

• Once CVDD is valid the clock drivers should be enabled. Although the clock inputs are not necessary at this time, they should either be

driven with a valid clock or held is a static state with one leg high and one leg low.

t2c

• The DDRCLK and REFCLK may begin to toggle anytime between when CVDD is at a valid level and the setup time before

goes high

POR

specified by t7.

• DVDD18 (1.8 V) supply is ramped up followed coincidentally by HHV (1.8 V).

• Filtered versions of 1.8 V can ramp simultaneously with DVDD18.

• RESETSTAT is driven low once the DVDD18 supply is available.

• All LVCMOS input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin

before DVDD18 is valid could cause damage to the device

t4a

• DVDD15 (1.5 V) supply is ramped up following DVDD18. Although ramping DVDD18 and DVDD15 simultaneously is permitted, the

voltage for DVDD15 must never exceed DVDD18.

t4b

•

may be driven high anytime after DVDD18 is at a valid level. In a

-controlled boot, both

RESET

RESETFULL

POR

and RESET must be high before RESETFULL is driven high.

•

must continue to remain low for at least 100 μs after power has stabilized.

POR

End Power Stabilization Phase

TMS320C6678 Peripheral Information and Electrical Specifications 105

ADVANCE INFORMATION

INFORMATION ADVANCE

TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691—November 2010				www.ti.com

Table 7-5			-Controlled Device Initialization — Core Before IO (Part 2 of 2)
		RESETFULL

Time	System State
t6	Begin Device Initialization Phase

• Device initialization requires 500 REFCLK periods after the Power Stabilization Phase. The maximum clock period is 33.33 nsec, so a delay of an additional 16 μs is required before a rising edge of POR. The clock must be active during the entire 16 μs. In RESETFULL-controlled boot, the RESETFULL signal will continue to be low after POR transitions high.


t7	• RESETFULL is held low for some period after POR has transitioned high.
t8	• The rising edge of the			will remove the reset to the efuse farm, allowing the scan to begin.
t8	• The rising edge of the		RESETFULL
	• Once device initialization and the efuse farm scan are complete, the					signal is driven high. This delay will be 10000 to 50000
					RESETSTAT	signal is driven high. This delay will be 10000 to 50000
		clock cycles.
	End Device Initialization Phase

End of Table 7-5

7.3.1.2.2 IO-Before-Core Power Sequencing

The timing diagram for core-before-IO power sequencing is shown in Figure 7-8 and defined in Table 7-6.

Figure 7-8 RESETFULL-Controlled Device Initialization — IO Before Core

	Power Stabilization Phase	C hip Initialization Phase
POR z		t7
		t7
R ESETFULLz
RESETz
C VDD(core AVS)		t5
t2b	t3a	t6
CVDD1 (core constant)	t2a	t6
DVDD18 (1.8V)	t4	t8
	t1	t8
	t1
DVDD15 (1.5V)		t3c
DVDD15 (1.5V)
	t3b

REFCLKP&N

D DRCLKP&N

RESETSTATz

RESETFULLz Controlled Reset Sequencing – IO before Core

106 TMS320C6678 Peripheral Information and Electrical Specifications

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