TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691—November 2010 |
www.ti.com |
|
7.4 Enhanced Direct Memory Access (EDMA3) Controller
The primary purpose of the EDMA3 is to service user-programmed data transfers between two memory-mapped slave endpoints on the device. The EDMA3 services software-driven paging transfers (e.g., data movement between external memory and internal memory), performs sorting or subframe extraction of various data structures, services event driven peripherals, and offloads data transfers from the device CPU.
There are 3 EDMA Channel Controllers on the C6678 DSP, TPCC0, TPCC1, and TPCC2. TPCC0 is optimized to be used for transfers to/from/within the MSMC and DDR-3 Subsytems. The others are to be used for the remaining traffic.
Each EDMA3 Channel Controller includes the following features:
ADVANCE |
|
– Single event can trigger transfer of array, frame, or entire block |
||
|
• Fully orthogonal transfer description |
|||
|
|
– |
3 transfer dimensions: |
|
|
|
|
› |
Array (multiple bytes) |
|
|
|
› |
Frame (multiple arrays) |
INFORMATION |
|
|
› |
Block (multiple frames) |
|
– Each PaRAM entry can be used as a DMA entry, QDMA entry, or link entry |
|||
|
|
– |
Independent indexes on source and destination |
|
|
• |
Flexible transfer definition: |
||
|
|
– Increment or FIFO transfer addressing modes |
||
|
|
– Linking mechanism allows for ping-pong buffering, circular buffering, and repetitive/continuous |
||
|
|
|
transfers, all with no CPU intervention |
|
|
|
– Chaining allows multiple transfers to execute with one event |
||
|
• 128 PaRAM entries for TPCC0, 512 each for TPCC1 and TPCC2 |
|||
|
|
– Used to define transfer context for channels |
||
|
• 16 DMA channels for TPCC0, 64 each for TPCC1 and TPCC2 |
|||
|
|
– Manually triggered (CPU writes to channel controller register), external event triggered, and chain |
||
|
|
|
triggered (completion of one transfer triggers another) |
|
|
• 8 Quick DMA (QDMA) channels per EDMA 3 Channel Controller |
|||
|
|
– Used for software-driven transfers |
||
|
|
– Triggered upon writing to a single PaRAM set entry |
||
|
• 2 transfer controllers and 2 event queues with programmable system-level priority for TPCC0, 4 transfer |
|||
|
|
controllers and 4 event queues with programmable system-level priority per channel controller for TPCC1 and |
||
|
|
TPCC2 |
||
|
• Interrupt generation for transfer completion and error conditions |
|||
|
• |
Debug visibility |
||
|
|
– Queue watermarking/threshold allows detection of maximum usage of event queues |
||
|
|
– Error and status recording to facilitate debug |
||
In the context of this document, TPTCs associated with TPCC0 are referred to as TPCC0 TPTC0 and1. TPTCs associated with TPCC1 and 2 are each referred to as TPCCx TPTC0 - 3, where x is 1 or 2. Each of the transfer controllers has a direct connection to the switched central resource (SCR). ‘‘DSP/2 Data SCR Connection Matrix’’ on page 82 and ‘‘DSP/3 Data SCR Connection Matrix’’ on page 82 lists the peripherals that can be accessed by the transfer controllers.
112 TMS320C6678 Peripheral Information and Electrical Specifications |
Copyright 2010 Texas Instruments Incorporated |
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
www.ti.com |
SPRS691—November 2010 |
|
7.4.1 EDMA3 Device-Specific Information
The EDMA supports two addressing modes: constant addressing and increment addressing mode. Constant addressing mode is applicable to a very limited set of use cases; for most applications increment mode can be used. On the C6678 DSP, the EDMA can use constant addressing mode only with the Enhanced Viterbi-Decoder Coprocessor (VCP) and the Enhanced Turbo Decoder Coprocessor (TCP). Constant addressing mode is not supported by any other peripheral or internal memory in the DSP. Note that increment mode is supported by all peripherals, including VCP and TCP. For more information on these two addressing modes, see the Enhanced Direct Memory Access 3 (EDMA3) for KeyStone Devices User Guide (literature number SPRUGS5).
For the range of memory addresses that include EDMA3 Channel Controller (TPCC) Control Registers and EDMA3 Transfer Controller (TPTC) Control Register see Section Table 2-2‘‘Memory Map Summary for TMS320C6678’’ on page 19. For memory offsets and other details on TPCC and TPTC Control Registers entries, see the Enhanced Direct Memory Access 3 (EDMA3) for KeyStone Devices User Guide (literature number SPRUGS5) for offset addresses on Parameter RAM (PaRAM) registers.
Table 7-11 |
EDMA3 Parameter RAM Contents |
|
|
|
|
|
|
PaRAM Set Number |
Offset Address |
Parameters (1) |
|
0 |
|
4000h to 401Fh |
PaRAM set 0 |
|
|
|
|
1 |
|
4020h to 403Fh |
PaRAM set 1 |
|
|
|
|
2 |
|
4040h to 405Fh |
PaRAM set 2 |
|
|
|
|
3 |
|
4060h to 407Fh |
PaRAM set 3 |
|
|
|
|
4 |
|
4080h to 409Fh |
PaRAM set 4 |
|
|
|
|
5 |
|
40A0h to 40BFh |
PaRAM set 5 |
|
|
|
|
6 |
|
40C0h to 40DFh |
PaRAM set 6 |
|
|
|
|
7 |
|
40E0h to 40FFh |
PaRAM set 7 |
|
|
|
|
8 |
|
4100h to 411Fh |
PaRAM set 8 |
|
|
|
|
9 |
|
4120h to 413Fh |
PaRAM set 9 |
|
|
|
|
... |
|
... |
... |
|
|
|
|
63 |
|
47E0h to 47FFh |
PaRAM set 63 |
|
|
|
|
64 |
|
4800h to 481Fh |
PaRAM set 64 |
|
|
|
|
65 |
|
4820h to 483Fh |
PaRAM set 65 |
|
|
|
|
... |
|
... |
... |
|
|
|
|
254 |
|
5FC0h to 5FDFh |
PaRAM set 254 |
|
|
|
|
255 |
|
5FE0h to 5FFFh |
PaRAM set 255 |
|
|
|
|
... |
|
... |
... |
|
|
|
|
510 |
|
7FC0h to 7FDFh |
PaRAM set 254 |
|
|
|
|
511 |
|
7FE0h to 7FFFh |
PaRAM set 255 |
|
|
|
|
1 A PaRAM set can be configured for use with either DMA channel, QDMA channel, or as a reload link set.
7.4.2 EDMA3 Channel Synchronization Events
The EDMA3 supports up to 16 DMA channels for TPCC0, 64 each for TPCC1 and TPCC2 that can be used to service system peripherals and to move data between system memories. DMA channels can be triggered by synchronization events generated by system peripherals. The following tables lists the source of the synchronization event associated with each of the EDMA TPCC DMA channels. On the C6678, the association of each synchronization event and DMA channel is fixed and cannot be reprogrammed.
ADVANCE INFORMATION
Copyright 2010 Texas Instruments Incorporated |
TMS320C6678 Peripheral Information and Electrical Specifications 113 |
INFORMATION ADVANCE
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691—November 2010 |
www.ti.com |
|
For more detailed information on the EDMA3 module and how EDMA3 events are enabled, captured, processed, prioritized, linked, chained, and cleared, etc., see the Enhanced Direct Memory Access 3 (EDMA3) for KeyStone Devices User Guide (literature number SPRUGS5).
Table 7-12 |
TPCC0 Events for C6678 |
|
|
Event Number |
|
Event |
Event Description |
0 |
|
TINT8L |
Timer 8 interrupt low |
|
|
|
|
1 |
|
TINT8H |
Timer 8 interrupt high |
|
|
|
|
2 |
|
TINT9L |
Timer 9 interrupt low |
|
|
|
|
3 |
|
TINT9H |
Timer 9 interrupt high |
|
|
|
|
4 |
|
TINT10L |
Timer 10 interrupt low |
|
|
|
|
5 |
|
TINT10H |
Timer 10 interrupt high |
|
|
|
|
6 |
|
TINT11L |
Timer 11 interrupt low |
|
|
|
|
7 |
|
TINT11H |
Timer 11 interrupt high |
|
|
|
|
8 |
|
INTC3_OUT0 |
Interrupt Controller Output |
|
|
|
|
9 |
|
INTC3_OUT1 |
Interrupt Controller Output |
|
|
|
|
10 |
|
INTC3_OUT2 |
Interrupt Controller Output |
|
|
|
|
11 |
|
INTC3_OUT3 |
Interrupt Controller Output |
|
|
|
|
12 |
|
INTC3_OUT4 |
Interrupt Controller Output |
|
|
|
|
13 |
|
INTC3_OUT5 |
Interrupt Controller Output |
|
|
|
|
14 |
|
INTC3_OUT6 |
Interrupt Controller Output |
|
|
|
|
15 |
|
INTC3_OUT7 |
Interrupt Controller Output |
|
|
|
|
End of Table 7-12 |
|
||
|
|
|
|
Table 7-13 |
TPCC1 Events for C6678 (Part 1 of 2) |
|
|
|||
Event Number |
|
Event |
Event Description |
|
|
|
0 |
|
|
SPIINT0 |
SPI interrupt |
|
|
|
|
|
|
|
|
|
1 |
|
|
SPIINT1 |
SPI interrupt |
|
|
|
|
|
|
|
|
|
2 |
|
|
SPIXEVT |
Transmit event |
|
|
|
|
|
|
|
|
|
3 |
|
|
SPIREVT |
Receive event |
|
|
|
|
|
|
|
|
|
4 |
|
|
I2CREVT |
I2C Receive event |
|
|
|
|
|
|
|
|
|
5 |
|
|
I2CXEVT |
I2C Transmit event |
|
|
|
|
|
|
|
|
|
6 |
|
|
GPINT0 |
GPIO Interrupt |
|
|
|
|
|
|
|
|
|
7 |
|
|
GPINT1 |
GPIO Interrupt |
|
|
|
|
|
|
|
|
|
8 |
|
|
GPINT2 |
GPIO Interrupt |
|
|
|
|
|
|
|
|
|
9 |
|
|
GPINT3 |
GPIO Interrupt |
|
|
|
|
|
|
|
|
|
10 |
|
|
GPINT4 |
GPIO Interrupt |
|
|
|
|
|
|
|
|
|
11 |
|
|
GPINT5 |
GPIO Interrupt |
|
|
|
|
|
|
|
|
|
12 |
|
|
GPINT6 |
GPIO Interrupt |
|
|
|
|
|
|
|
|
|
13 |
|
|
GPINT7 |
GPIO Interrupt |
|
|
|
|
|
|
|
|
|
14 |
|
|
SEMINT0 |
Semaphore interrupt |
|
|
|
|
|
|
|
|
|
15 |
|
|
SEMINT1 |
Semaphore interrupt |
|
|
|
|
|
|
|
|
|
16 |
|
|
SEMINT2 |
Semaphore interrupt |
|
|
|
|
|
|
|
|
|
17 |
|
|
SEMINT3 |
Semaphore interrupt |
|
|
|
|
|
|
|
|
|
18 |
|
|
SEMINT4 |
Semaphore interrupt |
|
|
|
|
|
|
|
|
|
19 |
|
|
SEMINT5 |
Semaphore interrupt |
|
|
|
|
|
|
|
|
|
20 |
|
|
SEMINT6 |
Semaphore interrupt |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
114 |
TMS320C6678 Peripheral Information and Electrical Specifications |
Copyright 2010 Texas Instruments Incorporated |
||||
|
|
|
TMS320C6678 |
|||
|
|
|
Multicore Fixed and Floating-Point Digital Signal Processor |
|||
www.ti.com |
|
|
SPRS691—November 2010 |
|||
|
|
|
|
|
|
|
Table 7-13 |
TPCC1 Events for C6678 (Part 2 of 2) |
|
|
|||
|
|
|
|
|
|
|
Event Number |
|
Event |
Event Description |
|
|
|
21 |
|
SEMINT7 |
Semaphore interrupt |
|
|
|
|
|
|
|
|
|
|
22 |
|
TINT8L |
Timer interrupt low |
|
|
|
|
|
|
|
|
|
|
23 |
|
TINT8H |
Timer interrupt high |
|
|
|
|
|
|
|
|
|
|
24 |
|
TINT9L |
Timer interrupt low |
|
|
|
|
|
|
|
|
|
|
25 |
|
TINT9H |
Timer interrupt high |
|
|
|
|
|
|
|
|
|
|
26 |
|
TINT10L |
Timer interrupt low |
|
|
|
|
|
|
|
|
|
|
27 |
|
TINT10H |
Timer interrupt high |
|
|
|
|
|
|
|
|
|
|
28 |
|
TINT11L |
Timer interrupt low |
|
|
INFORMATION |
|
|
|
|
|
|
|
29 |
|
TINT11H |
Timer interrupt high |
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
30 |
|
TINT12L |
Timer interrupt low |
|
|
|
|
|
|
|
|
|
|
31 |
|
TINT12H |
Timer interrupt high |
|
|
|
|
|
|
|
|
|
|
32 |
|
TINT13L |
Timer interrupt low |
|
|
|
|
|
|
|
|
|
|
33 |
|
TINT13H |
Timer interrupt high |
|
|
|
|
|
|
|
|
|
|
34 |
|
TINT14L |
Timer interrupt low |
|
|
|
|
|
|
|
|
|
|
35 |
|
TINT14H |
Timer interrupt high |
|
|
|
|
|
|
|
|
|
|
36 |
|
TINT15L |
Timer interrupt low |
|
|
|
|
|
|
|
|
|
|
37 |
|
TINT15H |
Timer interrupt high |
|
|
|
|
|
|
|
|
|
ADVANCE |
38 |
|
INTC2_OUT44 |
Interrupt Controller Output |
|
|
|
|
|
|
|
|
|
|
44 |
|
INTC2_OUT2 |
Interrupt Controller Output |
|
|
|
39 |
|
INTC2_OUT45 |
Interrupt Controller Output |
|
|
|
40 |
|
INTC2_OUT46 |
Interrupt Controller Output |
|
|
|
41 |
|
INTC2_OUT47 |
Interrupt Controller Output |
|
|
|
42 |
|
INTC2_OUT0 |
Interrupt Controller Output |
|
|
|
|
|
|
|
|
|
|
43 |
|
INTC2_OUT1 |
Interrupt Controller Output |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
45 |
|
INTC2_OUT3 |
Interrupt Controller Output |
|
|
|
|
|
|
|
|
|
|
46 |
|
INTC2_OUT4 |
Interrupt Controller Output |
|
|
|
|
|
|
|
|
|
|
47 |
|
INTC2_OUT5 |
Interrupt Controller Output |
|
|
|
|
|
|
|
|
|
|
48 |
|
INTC2_OUT6 |
Interrupt Controller Output |
|
|
|
|
|
|
|
|
|
|
49 |
|
INTC2_OUT7 |
Interrupt Controller Output |
|
|
|
|
|
|
|
|
|
|
50 |
|
INTC2_OUT8 |
Interrupt Controller Output |
|
|
|
|
|
|
|
|
|
|
51 |
|
INTC2_OUT9 |
Interrupt Controller Output |
|
|
|
|
|
|
|
|
|
|
52 |
|
INTC2_OUT10 |
Interrupt Controller Output |
|
|
|
|
|
|
|
|
|
|
53 |
|
INTC2_OUT11 |
Interrupt Controller Output |
|
|
|
|
|
|
|
|
|
|
54 |
|
INTC2_OUT12 |
Interrupt Controller Output |
|
|
|
|
|
|
|
|
|
|
55 |
|
INTC2_OUT13 |
Interrupt Controller Output |
|
|
|
|
|
|
|
|
|
|
56 |
|
INTC2_OUT14 |
Interrupt Controller Output |
|
|
|
|
|
|
|
|
|
|
57 |
|
INTC2_OUT15 |
Interrupt Controller Output |
|
|
|
|
|
|
|
|
|
|
58 |
|
INTC2_OUT16 |
Interrupt Controller Output |
|
|
|
|
|
|
|
|
|
|
59 |
|
INTC2_OUT17 |
Interrupt Controller Output |
|
|
|
|
|
|
|
|
|
|
60 |
|
INTC2_OUT18 |
Interrupt Controller Output |
|
|
|
|
|
|
|
|
|
|
61 |
|
INTC2_OUT19 |
Interrupt Controller Output |
|
|
|
|
|
|
|
|
|
|
62 |
|
INTC2_OUT20 |
Interrupt Controller Output |
|
|
|
|
|
|
|
|
|
|
63 |
|
INTC2_OUT21 |
Interrupt Controller Output |
|
|
|
|
|
|
|
|
|
|
End of Table 7-13 |
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Copyright 2010 Texas Instruments Incorporated |
TMS320C6678 Peripheral Information and Electrical Specifications |
115 |
|
|||
|
TMS320C6678 |
|
|
|
|||
|
Multicore Fixed and Floating-Point Digital Signal Processor |
|
|
||||
|
SPRS691—November 2010 |
|
|
www.ti.com |
|||
|
|
|
|
|
|
|
|
|
Table 7-14 |
TPCC3 Events for C6678 (Part 1 of 2) |
|
|
|||
|
|
|
|
|
|
|
|
|
Event Number |
|
Event |
Event Description |
|
|
|
|
0 |
|
|
SPIINT0 |
SPI interrupt |
|
|
|
|
|
|
|
|
|
|
|
1 |
|
|
SPIINT1 |
SPI interrupt |
|
|
|
|
|
|
|
|
|
|
|
2 |
|
|
SPIXEVT |
Transmit event |
|
|
|
|
|
|
|
|
|
|
|
3 |
|
|
SPIREVT |
Receive event |
|
|
|
|
|
|
|
|
|
|
|
4 |
|
|
I2CREVT |
I2C Receive event |
|
|
|
|
|
|
|
|
|
|
|
5 |
|
|
I2CXEVT |
I2C Transmit event |
|
|
|
|
|
|
|
|
|
|
|
6 |
|
|
GPINT0 |
GPIO Interrupt |
|
|
|
|
|
|
|
|
|
|
ADVANCE |
7 |
|
|
GPINT1 |
GPIO Interrupt |
|
|
|
|
|
|
|
|
|
|
8 |
|
|
GPINT2 |
GPIO Interrupt |
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
9 |
|
|
GPINT3 |
GPIO Interrupt |
|
|
|
|
|
|
|
|
|
|
|
10 |
|
|
GPINT4 |
GPIO Interrupt |
|
|
|
|
|
|
|
|
|
|
|
11 |
|
|
GPINT5 |
GPIO Interrupt |
|
|
|
|
|
|
|
|
|
|
|
12 |
|
|
GPINT6 |
GPIO Interrupt |
|
|
|
|
|
|
|
|
|
|
INFORMATION |
13 |
|
|
GPINT7 |
GPIO Interrupt |
|
|
|
|
|
|
|
|
|
|
14 |
|
|
SEMINT0 |
Semaphore interrupt |
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
15 |
|
|
SEMINT1 |
Semaphore interrupt |
|
|
|
|
|
|
|
|
|
|
|
16 |
|
|
SEMINT2 |
Semaphore interrupt |
|
|
|
|
|
|
|
|
|
|
|
17 |
|
|
SEMINT3 |
Semaphore interrupt |
|
|
|
|
|
|
|
|
|
|
|
18 |
|
|
SEMINT4 |
Semaphore interrupt |
|
|
|
|
|
|
|
|
|
|
|
19 |
|
|
SEMINT5 |
Semaphore interrupt |
|
|
|
|
|
|
|
|
|
|
|
20 |
|
|
SEMINT6 |
Semaphore interrupt |
|
|
|
|
|
|
|
|
|
|
|
21 |
|
|
SEMINT7 |
Semaphore interrupt |
|
|
|
|
|
|
|
|
|
|
|
22 |
|
|
TINT8L |
Timer interrupt low |
|
|
|
|
|
|
|
|
|
|
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23 |
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TINT8H |
Timer interrupt high |
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24 |
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TINT9L |
Timer interrupt low |
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25 |
|
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TINT9H |
Timer interrupt high |
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26 |
|
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TINT10L |
Timer interrupt low |
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27 |
|
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TINT10H |
Timer interrupt high |
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28 |
|
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TINT11L |
Timer interrupt low |
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29 |
|
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TINT11H |
Timer interrupt high |
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30 |
|
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TINT12L |
Timer interrupt low |
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31 |
|
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TINT12H |
Timer interrupt high |
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32 |
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TINT13L |
Timer interrupt low |
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33 |
|
|
TINT13H |
Timer interrupt high |
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34 |
|
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TINT14L |
Timer interrupt low |
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35 |
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TINT14H |
Timer interrupt high |
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36 |
|
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TINT15L |
Timer interrupt low |
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37 |
|
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TINT15H |
Timer interrupt high |
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38 |
|
|
INTC2_OUT48 |
Interrupt Controller Output |
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39 |
|
|
INTC2_OUT49 |
Interrupt Controller Output |
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40 |
|
|
URXEVT |
UART Receive event |
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41 |
|
|
UTXEVT |
UART Transmit event |
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42 |
|
|
INTC2_OUT22 |
Interrupt Controller Output |
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43 |
|
|
INTC2_OUT23 |
Interrupt Controller Output |
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116 |
TMS320C6678 Peripheral Information and Electrical Specifications |
Copyright 2010 Texas Instruments Incorporated |
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