INFORMATION ADVANCE
TMS320C6678 |
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Multicore Fixed and Floating-Point Digital Signal Processor |
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SPRS691—November 2010 |
www.ti.com |
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Table 3-15 |
IPC Generation Registers (IPCGRH) Field Descriptions |
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Bit |
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Field |
Description |
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31-4 |
SRCSx |
Reads return current value of internal register bit. |
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Writes: |
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0 = No effect |
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1 = Sets both SRCSx and the corresponding SRCCx. |
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3-1 |
Reserved |
Reserved |
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0 |
IPCG |
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Reads return 0. |
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Writes:
0 = No effect
1 = Creates an interrupt pulse on device pin (host interrupt/event output in HOUT pin)
End of Table 3-15
3.3.15 IPC Acknowledgement Host (IPCARH) Register
IPCARH registers are provided to facilitate host DSP interrupt. Operation and use of IPCARH is the same as other IPCAR registers. The IPC Acknowledgement Host Register is shown in Figure 3-14 and described in Table 3-16.
Figure 3-14 IPC Acknowledgement Register (IPCARH)
31 |
30 |
29 |
28 |
27 |
8 |
7 |
6 |
5 |
4 |
3 |
0 |
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SRCC27 |
SRCC26 |
SRCC25 |
SRCC24 |
SRCC23 – SRCC4 |
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SRCC3 |
SRCC2 |
RCC1 |
SRCC0 |
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Reserved |
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RW +0 |
RW +0 |
RW +0 |
RW +0 |
RW +0 (per bit field) |
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RW +0 |
RW +0 |
RW +0 |
RW +0 |
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R, +0000 |
Legend: R = Read only; RW = Read/Write; -n = value after reset |
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Table 3-16 |
IPC Acknowledgement Register (IPCARH) Field Descriptions |
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Bit |
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Field |
Description |
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31-4 |
SRCCx |
Reads return current value of internal register bit. |
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Writes: |
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0 |
= No effect |
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1 |
= Clears both SRCCx and the corresponding SRCSx |
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3-0 |
Reserved |
Reserved |
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End of Table 3-16 |
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74 |
Device Configuration |
Copyright 2010 Texas Instruments Incorporated |
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
www.ti.com |
SPRS691—November 2010 |
|
3.3.16 Timer Input Selection Register (TINPSEL)
Timer input selection is handled within the control register TINPSEL. The Timer Input Selection Register is shown in Figure 3-15 and described in Table 3-17.
Figure 3-15 Timer Input Selection Register (TINPSEL)
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31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
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22 |
21 |
20 |
19 |
18 |
17 |
16 |
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TINPH |
TINPL |
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TINPH |
TINPL |
TINPH |
TINPL |
TINPH |
TINPL |
TINPH |
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TINPL |
TINPH |
TINPL |
TINPH |
TINPL |
TINPH |
TINPL |
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SEL15 |
SEL15 |
SEL14 |
SEL14 |
SEL13 |
SEL13 |
SEL12 |
SEL12 |
SEL11 |
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SEL11 |
SEL10 |
SEL10 |
SEL9 |
SEL9 |
SEL8 |
SEL8 |
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RW, |
RW, |
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RW, |
RW, |
RW, |
RW, |
RW, |
RW, |
RW, |
RW, |
RW, |
RW, |
RW, |
RW, |
RW, |
RW, |
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+1 |
+0 |
+1 |
+0 |
+1 |
+0 |
+1 |
+0 |
+1 |
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+0 |
+1 |
+0 |
+1 |
+1 |
+1 |
+0 |
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15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
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6 |
5 |
4 |
3 |
2 |
1 |
0 |
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TINPH |
TINPL |
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TINPH |
TINPL |
TINPH |
TINPL |
TINPH |
TINPL |
TINPH |
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TINPL |
TINPH |
TINPL |
TINPH |
TINPL |
TINPH |
TINPL |
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SEL7 |
SEL7 |
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SEL6 |
SEL6 |
SEL5 |
SEL5 |
SEL4 |
SEL4 |
SEL3 |
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SEL3 |
SEL2 |
SEL2 |
SEL1 |
SEL1 |
SEL0 |
SEL0 |
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RW, |
RW, |
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RW, |
RW, |
RW, |
RW, |
RW, |
RW, |
RW, |
RW, |
RW, |
RW, |
RW, |
RW, |
RW, |
RW, |
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+1 |
+0 |
+1 |
+0 |
+1 |
+0 |
+1 |
+0 |
+1 |
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+0 |
+1 |
+0 |
+1 |
+1 |
+1 |
+0 |
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Legend: R = Read only; RW = Read/Write; -n = value after reset |
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Table 3-17 |
Timer Input Selection Field Description (TINPSEL) (Part 1 of 3) |
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Bit |
Field |
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Description |
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31 |
TINPHSEL15 |
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Input select for TIMER15 high. |
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0 |
= TIMI0 |
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1 |
= TIMI1 |
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30 |
TINPLSEL15 |
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Input select for TIMER15 low. |
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0 |
= TIMI0 |
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1 |
= TIMI1 |
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29 |
TINPHSEL14 |
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Input select for TIMER14 high. |
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0 |
= TIMI0 |
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1 |
= TIMI1 |
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28 |
TINPLSEL14 |
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Input select for TIMER14 low. |
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0 |
= TIMI0 |
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1 |
= TIMI1 |
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27 |
TINPHSEL13 |
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Input select for TIMER13 high. |
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0 |
= TIMI0 |
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1 |
= TIMI1 |
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26 |
TINPLSEL13 |
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Input select for TIMER13 low. |
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0 |
= TIMI0 |
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1 |
= TIMI1 |
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25 |
TINPHSEL12 |
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Input select for TIMER12 high. |
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0 |
= TIMI0 |
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1 |
= TIMI1 |
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24 |
TINPLSEL12 |
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Input select for TIMER12 low. |
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0 |
= TIMI0 |
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1 |
= TIMI1 |
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23 |
TINPHSEL11 |
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Input select for TIMER11 high. |
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0 |
= TIMI0 |
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1 |
= TIMI1 |
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22 |
TINPLSEL11 |
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Input select for TIMER11 low. |
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0 |
= TIMI0 |
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1 |
= TIMI1 |
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ADVANCE INFORMATION
Copyright 2010 Texas Instruments Incorporated |
Device Configuration |
75 |
INFORMATION ADVANCE
TMS320C6678 |
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||
Multicore Fixed and Floating-Point Digital Signal Processor |
|
|||
SPRS691—November 2010 |
www.ti.com |
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Table 3-17 |
Timer Input Selection Field Description (TINPSEL) (Part 2 of 3) |
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Bit |
Field |
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Description |
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21 |
TINPHSEL10 |
Input select for TIMER10 high. |
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0 = TIMI0 |
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1 = TIMI1 |
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20 |
TINPLSEL10 |
Input select for TIMER10 low. |
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0 = TIMI0 |
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1 = TIMI1 |
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19 |
TINPHSEL9 |
Input select for TIMER9 high. |
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0 = TIMI0 |
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1 = TIMI1 |
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18 |
TINPLSEL9 |
Input select for TIMER9 low. |
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0 = TIMI0 |
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1 = TIMI1 |
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17 |
TINPHSEL8 |
Input select for TIMER8 high. |
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0 = TIMI0 |
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1 = TIMI1 |
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16 |
TINPLSEL8 |
Input select for TIMER8 low. |
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0 = TIMI0 |
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1 = TIMI1 |
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15 |
TINPHSEL7 |
Input select for TIMER7 high. |
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0 = TIMI0 |
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1 = TIMI1 |
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14 |
TINPLSEL7 |
Input select for TIMER7 low. |
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0 = TIMI0 |
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1 = TIMI1 |
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13 |
TINPHSEL6 |
Input select for TIMER6 high. |
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0 = TIMI0 |
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1 = TIMI1 |
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12 |
TINPLSEL6 |
Input select for TIMER6 low. |
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0 = TIMI0 |
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1 = TIMI1 |
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11 |
TINPHSEL5 |
Input select for TIMER5 high. |
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0 = TIMI0 |
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1 = TIMI1 |
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10 |
TINPLSEL5 |
Input select for TIMER5 low. |
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0 = TIMI0 |
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1 = TIMI1 |
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9 |
TINPHSEL4 |
Input select for TIMER4 high. |
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0 = TIMI0 |
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1 = TIMI1 |
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8 |
TINPLSEL4 |
Input select for TIMER4 low. |
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0 = TIMI0 |
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1 = TIMI1 |
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7 |
TINPHSEL3 |
Input select for TIMER3 high. |
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0 = TIMI0 |
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1 = TIMI1 |
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6 |
TINPLSEL3 |
Input select for TIMER3 low. |
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0 = TIMI0 |
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1 = TIMI1 |
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5 |
TINPHSEL2 |
Input select for TIMER2 high. |
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0 = TIMI0 |
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1 = TIMI1 |
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76 |
Device Configuration |
Copyright 2010 Texas Instruments Incorporated |
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|
|
TMS320C6678 |
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|
|
|
Multicore Fixed and Floating-Point Digital Signal Processor |
www.ti.com |
|
|
SPRS691—November 2010 |
|
|
|
|
||
Table 3-17 |
Timer Input Selection Field Description (TINPSEL) (Part 3 of 3) |
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Bit |
Field |
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Description |
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4 |
TINPLSEL2 |
Input select for TIMER2 low. |
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0 |
= TIMI0 |
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1 |
= TIMI1 |
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3 |
TINPHSEL1 |
Input select for TIMER1 high. |
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0 |
= TIMI0 |
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1 |
= TIMI1 |
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2 |
TINPLSEL1 |
Input select for TIMER1 low. |
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0 |
= TIMI0 |
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1 |
= TIMI1 |
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1 |
TINPHSEL0 |
Input select for TIMER0 high. |
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0 |
= TIMI0 |
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1 |
= TIMI1 |
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0 |
TINPLSEL0 |
Input select for TIMER0 low. |
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0 |
= TIMI0 |
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1 |
= TIMI1 Legend: |
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End of Table 3-17 |
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3.3.17 Timer Output Selection Register (TOUTPSEL)
The timer output selection is handled within the control register TOUTSEL. The Timer Output Selection Register is shown in Figure 3-16 and described in Table 3-18.
Figure 3-16 Timer Output Selection Register (TOUTPSEL)
31 |
10 |
9 |
5 |
4 |
0 |
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Reserved |
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TOUTPSEL1 |
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TOUTPSEL0 |
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R,+000000000000000000000000 |
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RW,+00001 |
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RW,+00000 |
Legend: R = Read only; RW = Read/Write; -n = value after reset |
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Table 3-18 |
Timer Output Selection Field Description (TOUTPSEL) (Part 1 of 2) |
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Bit |
Field |
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Description |
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31-9 |
Reserved |
Reserved |
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9-5 |
TOUTPSEL1 |
Output select for TIMO1 |
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00000: TOUTL0 |
10000: TOUTL8 |
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00001: TOUTH0 |
10001: TOUTH8 |
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00010: TOUTL1 |
10010: TOUTL9 |
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00011: TOUTH1 |
10011: TOUTH9 |
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00100: TOUTL2 |
10100: TOUTL10 |
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00101: TOUTH2 |
10101: TOUTH10 |
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00110: TOUTL3 |
10110: TOUTL11 |
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00111: TOUTH3 |
10111: TOUTH11 |
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01000: TOUTL4 |
11000: TOUTL12 |
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01001: TOUTH4 |
11001: TOUTH12 |
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01010: TOUTL5 |
11010: TOUTL13 |
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01011: TOUTH5 |
11011: TOUTH13 |
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01100: TOUTL6 |
11100: TOUTL14 |
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01101: TOUTH6 |
11101: TOUTH14 |
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01110: TOUTL7 |
11110: TOUTL15 |
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01111: TOUTH7 |
11111: TOUTH15 |
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ADVANCE INFORMATION
Copyright 2010 Texas Instruments Incorporated |
Device Configuration |
77 |